{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

ece3803_d2008_hw3_solutions

# ece3803_d2008_hw3_solutions - ECE 3803 D2008 Homework 3...

This preview shows pages 1–3. Sign up to view the full content.

ECE 3803 D2008 Homework 3 solutions 1 ECE 3803 D2008: Microprocessor System Design Homework 3 solutions SRAM, write bus cycle timing 1. [50 pts] This problem is concerned with the attached CPU + SRAM circuit diagram. Assume: Room temperature operation V DDCORE = 3.3 V V DDIO = 3.3 V (also applies to all external devices) Load capacitance on all CPU outputs = 30 pF 30 MHz CPU clock 45 ns version of the SRAM a. [20 pts] Assuming the SRAM write pulse width is the timing bottleneck, determine the minimum number of wait states required in the SRAM write bus cycle. SRAM spec: t PWE (min) = 35 ns CPU: Derating factors for the EBI: δ (room temp) = 1 δ VDDCORE (3.3V) = 1 δ VDDIO (3.3V) = 1 clock period T = 1/30 MHz = 33.3 ns write pulse width on CPU: EBI 19 w/o wait states EBI 20 w/ wait states EBI 19 (min) = 1*(1*(t CHMCK – 0.9ns) + 1*30pF*(-0.01ns/pF)) clock high half-period t CHMCK (min) = 0.45*T = 0.45*33.3ns = 15.0 ns EBI 19 (min) = ((15.0ns – 0.9ns) + 30pF*(-0.01ns/pF)) = 13.8 ns < 35 ns barb2right wait states needed w/ n wait states: EBI 20 (min) = 1*(1*(n * t CPMCK – 1.0ns) + 1*30pF*(-0.01ns/pF)) = n * 33.3ns – 1.3ns to satisfy SRAM timing specs, we need to make sure EBI 20 (min) t PWE (min) n * 33.3ns – 1.3ns 35ns n * 33.3ns 36.3ns n 36.3ns/33.3ns = 1.09 rounding up, n (min) = 2 wait states

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
ECE 3803 D2008 Homework 3 solutions 2 b. [10 pts] Determine the SRAM data setup time with the wait states computed in part (a), and add more wait states if required. SRAM spec: t SD (min) = 25 ns CPU: EBI 16 w/o wait states EBI 17 w/ wait states Since we already need 1 wait state, EBI 17 (min) = 1*(1*(n * t CPMCK – 0.3ns) + 1*30pF*(-0.045ns/pF) + 1*30pF*(0.035ns/pF)) = n * 33.3ns – 0.6ns = 2 * 33.3ns – 0.6ns = 66.0 > 25 ns barb2right all set w/ 2 wait states c. [10 pts] Determine if the SRAM CE setup time is satisfied with the number of wait states from part (b), and add more if required. SRAM spec: t SCE (min) = 40 ns CPU (w/ n > 0 wait states): Minimum time from NCS to NWR = n * T + t CLMCK (min) + EBI 10 (min) – EBI 4 (max) t CLMCK (min) = 0.45*T = 0.45*33.3ns = 15.0 ns EBI 10 (min) = 1*(1*8.3ns + 1*30pF*(0.022ns/pF)) = 9.0 ns EBI 4 (max) = 1*(1*17.6ns + 1*30pF*(0.045ns/pF)) = 19.0 ns Minimum time from NCS to NWR w/ 1 wait state = 2 * 33.3ns + 18.0ns + 9.0ns – 19.0ns = 74.6 ns > 40 ns barb2right all set w/ 2 wait states
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 6

ece3803_d2008_hw3_solutions - ECE 3803 D2008 Homework 3...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online