ECE
ece475-l5

ece475-l5 - ECE 475/ECE 416 Computer Architecture...

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1 ECE 475/ECE 416 Computer Architecture - Pipelining Edward Suh C omputer S ystems L aboratory [email protected] ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 2 Review / Overview ± MIPS ISA Designed for efficient implementation with pipeline ± Let’s discuss how to build a simple pipelined processor for MIPS ISA What is pipelining? How to apply the pipelining to a processor design? What are the challenges in processor pipelining? Data hazards Control hazards Structural hazards

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2 ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 3 Forget circuits… lets solve a “Real Problem” Device: Washer Function: Fill, Agitate, Spin Washer PD = 30 mins Device: Dryer Function: Heat, Spin Dryer PD = 60 mins INPUT: dirty laundry OUTPUT: 6 more weeks ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 4 Step 1: Step 2: Total = Washer PD + Dryer PD = _________ mins One load at a time Everyone knows that the real reason that Cornell students put off doing laundry so long is not because they procrastinate, are lazy, or even have better things to do. The fact is, doing one load at a time is not smart.
3 ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 5 Doing N loads of laundry Here’s how they do laundry at other schools, the “combinational” way. Step 1: Step 2: Step 3: Step 4: Total = N*(Washer PD + Dryer PD ) = ____________ mins ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 6 Doing N Loads… the Cornell way Cornell students “pipeline” the laundry process. That’s why we wait! Step 1: Step 2: Step 3: Total = N * Max(Washer PD , Dryer PD ) = ____________ mins Actually, it’s more like N*60 + 30 if we account for the startup transient correctly. When doing pipeline analysis, we’re mostly interested in the “steady state” where we assume we have an infinite supply of inputs.

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4 ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 7 Performance Measures Latency: The delay from when an input is established until the output associated with that input becomes valid. (Unpipelined Laundry = _________ mins) ( Cornell Laundry = _________ mins) Throughput: The rate of which inputs or outputs are processed. (Unpipelined Laundry = _________ outputs/min) ( Cornell Laundry = _________ outputs/min) Assuming that the wash is started as soon as possible and waits (wet) in the washer until dryer is available. ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 8 Okay, back to circuits… F G H X P(X) For combinational logic: latency = t PD , throughput = 1/t PD. We can’t get the answer faster, but are we making effective use of our hardware at all times? G(X) F(X) P(X) X F & G are “idle”, just holding their outputs stable while H performs its computation
5 ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 9 Pipelined Circuits use registers to hold H’s input stable!

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