ece475-l7 - ECE 475/CS 416 Computer Architecture Dynamic...

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1 ECE 475/CS 416 Computer Architecture - Dynamic Scheduling I Edward Suh C omputer S ystems L aboratory [email protected] ECE 475/CS 416 — Computer Architecture, Fall 2007 2 Review ± Need to support precise exceptions for re-startable exceptions Wait till the commit point (MEM/WB) in the 5-stage pipeline ± Cannot increase pipeline depth forever CPI eventually begins to increase due to stalls ± Complex pipelining is required for real systems, but introduces difficult challenges Long latency floating point units, multiple functional units, real memory system More structural/RAW hazards, WAR/WAW hazards, exception handling
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 3 Instruction-Level Parallelism ± ILP: the potential to overlap the execution of multiple instructions from a sequential stream to improve performance it is a property of the code ± ILP techniques: reduce pipeline stalls by exploiting existing ILP ± Pipeline stalls caused by structural hazards (true) data dependences – RAW name dependences – WAR, WAW control dependences [Note: for this class, let’s forget about delay slots] control data structural ideal stall stall stall CPI CPI + + + = ECE 475/CS 416 — Computer Architecture, Fall 2007 4 RAW dependences WAR , WAW dependences ld $2, A($1) ld $2, A($1) add $3, $3, $2 add $3, $3, $2 st $3, C($1) st $3, C($1) ld $2, B($1) ld $2, B($1) add $3, $3, $2 add $3, $3, $2 st $3, D($1) st $3, D($1) ± Can compiler eliminate some data dependences? True vs. Name Dependences
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 5 True vs. Name Dependences RAW dependences WAR , WAW dependences ld $2, A($1) ld $2, A($1) add $3, $3, $2 add $3, $3, $2 st $3, C($1) st $3, C($1) ld $4 , B($1) ld $4 , B($1) ; $4 for $2 add $5 , $3, $4 add $5 , $3, $4 ; $5 for $3 st $5 , D($1) st $5 , D($1) ± WAR, WAW name dependences – no actual dataflow ± renaming increased register pressure number of ISA registers limited can backfire – register spill hardware will have to make up for this… ECE 475/CS 416 — Computer Architecture, Fall 2007 6 Control Dependences ± Preserving data dependences alone not enough add $1 , $2, $3 beq $1, $4, L sub $1 , $5, $6 ; (not a delay slot) L: mult $7, $1 , 16 ± Must make sure the correct value gets read ± Data+control dependences preserve dataflow
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007 7 Dynamic Scheduling ± Allow hardware to make scheduling decisions ± Advantages: simpler compiler handles cases not resolvable at compile time can run same code on different (ISA-compatible) pipeline ± Disadvantages: hardware complexity significantly higher ECE 475/CS 416 — Computer Architecture, Fall 2007 8 Complex Pipeline Structure IF ID WB ALU Mem Fadd Fmul Fdiv GPR’s FPR’s
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5 ECE 475/CS 416 — Computer Architecture, Fall 2007 9 When is it Safe to Issue an Instruction? Suppose a data structure keeps track of all the instructions in all the functional units The following checks need to be made before the Issue stage can dispatch an instruction • Is the required function unit available?
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