ece475-l10 - ECE 475/CS 416 Computer Architecture - Caches...

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1 ECE 475/CS 416 Computer Architecture - Caches and Memory II Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements ± About the feedback • Lecture notes online: www.csl.cornell.edu/courses/ece475/resources.html • Room temperature: facility people are working on it • Lecture: keep 5 min break, announcement at the beginning • HW / Labs ± HW1 solution updates • 1.3 d) • 1.4 d) ± Prelim conflict?
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review ± Memory hierarchy basics • Memory technologies • Principle of locality ± Caches • Concepts: block, write policy, associativity, block replacement • Performance estimation: average memory access time ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Improving Cache Performance Average memory access time = Hit time + Miss rate x Miss penalty To improve performance: • reduce the hit time • reduce the miss rate • reduce the miss penalty • (increase the bandwidth) What is the simplest design strategy? Biggest cache that doesn’t increase hit time past 1-2 cycles (approx 8-32KB in modern technology)
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Improving Cache Performance ± Decrease Hit Time ± Decrease Miss Rate ± Decrease Miss Penalty ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Small, Simple Caches ± On many machines today the cache access sets the cycle time ± Hit time is therefore important beyond its effect on AMAT ± Index portion of address reads cache tag for comparison • this part of the hit time is the most time consuming • smaller hardware is faster, use small 1 st -level caches • 1 st -level caches also have to be on chip, again small • compromise: tags on chip, data off ± Simple caches (direct-mapped) also have better hit times • tag access overlapped with data access • 1.2-1.5 times faster than two-way set associative
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Way Predicting Caches (MIPS R10000 L2) ± Use processor address to index into way prediction table ± Look in predicted way at given index, then: HIT MISS Return copy of data from cache Look in other way Read block of data from next level of cache MISS SLOW HIT (change entry in prediction table) ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Improving Cache Performance ± Decrease Hit Time ± Decrease Miss Rate ± Decrease Miss Penalty
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5 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Causes for Cache Misses Compulsory: first-reference to a block a.k.a. cold start misses - misses that would occur even with infinite cache Capacity: cache is too small to hold all data needed by the program - misses that would occur even under perfect placement & replacement policy Conflict: misses that occur because of collisions due to block-placement strategy - misses that would not occur with full associativity ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Effect of Cache Parameters • Larger cache size
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This note was uploaded on 02/19/2008 for the course ECE 4750 taught by Professor Suh during the Fall '07 term at Cornell University (Engineering School).

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ece475-l10 - ECE 475/CS 416 Computer Architecture - Caches...

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