ece475-l20 - ECE 475/CS 416 Computer Architecture - Snoopy...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE 475/CS 416 Computer Architecture - Snoopy Cache Coherence Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements ± HW3 is graded • Re-grade request till Nov 20th ± Thursday’s lecture: Professor Jose Martinez • Directory based cache coherency
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review ± Taxonomy of parallel computers • Processing elements: (SISD), SIMD, MIMD • Communication: message passing vs. shared memory ± Memory model: sequential consistency ± Critical section: mutual exclusion • Locks and semaphore ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Memory Fences Instructions to sequentialize memory accesses Processors with relaxed or weak memory models (i.e., permit Loads and Stores to different addresses to be reordered) need to provide memory fence instructions to force the serialization of memory accesses Examples of processors with relaxed memory models: Sparc V8 (TSO,PSO): Membar Sparc V9 (RMO): Membar #LoadLoad, Membar #LoadStore Membar #StoreLoad, Membar #StoreStore PowerPC (WO): Sync, EIEIO Memory fences are expensive operations, however, one pays the cost of serialization only when it is required
Background image of page 2
3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Using Memory Fences Producer posting Item x: Load R tail , (tail) Store (R tail ), x Membar SS R tail =R tail +1 Store (tail), R tail Consumer: Load R head , (head) spin: Load R tail , (tail) if R head ==R tail goto spin Membar LL Load R, (R head ) R head =R head +1 Store (head), R head process(R) Producer Consumer tail head R tail R tail R head R ensures that tail ptr is not updated before x has been stored ensures that R is not loaded before x has been stored ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Memory Consistency in SMPs Suppose CPU-1 updates A to 200 . write-back : memory and cache-2 have stale values write-through : cache-2 has a stale value Do these stale values matter?
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 11

ece475-l20 - ECE 475/CS 416 Computer Architecture - Snoopy...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online