ece475-l4 - ECE 475/CS 416 Computer Architecture - MIPS ISA...

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1 ECE 475/CS 416 Computer Architecture - MIPS ISA Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 2 Review ± Instruction Set Architecture (ISA) is the HW/SW interface • Efficient implementation • Efficiency as a compiler target ± Classifying ISAs • Internal storage: accumulator, stack, registers • Memory addressing modes: direct, indirect, displacement, etc. • Encoding: fixed vs. variable • Etc.
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 3 MIPS Architectural Approach ± Load/store or register-register instruction set Only operate on data in registers Register operations affect the entire contents of register No partial register writes except for single-precision FP Only load/store instructions access memory True in all RISC instruction sets True in all instruction sets designed since 1980 ± Emphasis on efficient implementation Make the common case fast ± Simplicity: provide primitives rather than solution Simplicity favors regularity ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 4 MIPS Data Types ± Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word ± Character supported as a byte (signed or unsigned) ± Integers 2's Complement ± Floating Point: M x 2 E single precision double precision
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 5 MIPS Storage Model ± 2 32 bytes of memory: accessible by loads/stores ± 31 x 32-bit GPRs (R0 = 0) or integer multiply/divide • why only 32 registers? Smaller is faster ± PC: incremented by 4 for each instruction • except for branch, j, jal 0 $0 $1 ° ° ° $31 PC lo hi $f0 $f1 ° ° ° $f31 $f30 FP registers are paired for double-precision. Specify the even register, which holds the less-significant word. ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 6 MIPS Memory Access ± All memory access through loads and stores ± Aligned words, halfwords, and bytes • A halfword or byte loaded from memory can be sign- or zero-extended to form a word in the destination register ± Floating-point loads/stores for FP registers ± Single addressing mode (displacement or based) 16-bit sign-extended displacement (immediate f eld) + register = memory address ± In addition: • Displacement = 0 uses register contents as address • Register = 0 uses 16-bit displacement as address Registers + Memory Data to load/ location to store into
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007, Suh 7 MIPS Load/Store Instructions Instruction Example Meaning Comments store word sw $3, 8($4) Mem[$4+8]=$3 Store word store halfword sh $3, 6($2) Mem[$2+6]=$3 Stores only lower 16 bits store byte sb $2, 7($3) Mem[$3+7]=$3 Stores only lowest byte store float sf $f2, 4($2) Mem[$2+4]=$f2 Store FP word load word lw $1, 8($2) $1=Mem[8+$2] Load word load halfword lh $1, 6($3) $1=Mem[6+$3] Load half; sign extend load half unsign lhu $1, 6($3) $1=Mem[6+$3] Load half; zero extend load byte lb $1, 5($3) $1=Mem[5+$3] Load byte; sign extend load byte unsign
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ece475-l4 - ECE 475/CS 416 Computer Architecture - MIPS ISA...

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