ece475-l22 - ECE 475/CS 416 Computer Architecture - Relaxed...

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ECE 475/CS 416 Computer Architecture - Relaxed Memory Model Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements Lab3 is graded • Re-grade request till Nov 29th No class on Thursday
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ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review Sequential consistency • Memory ordering • Cache coherence Cache coherence protocol • Snoopy • Directory-based ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Sequential Consistency In-order instruction execution Atomic loads and stores SC is easy to understand but architects and compiler writers want to violate it for performance Processor 1 Processor 2 Store ( a) , 10; L: Load r1, ( flag ); Store ( flag ), 1; if r 1 == 0 goto L; Load r2, ( a ); initially flag = 0
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ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Memory Model Issues Architectural optimizations that are correct for uniprocessors, often violate sequential consistency and result in a new memory model for multiprocessors ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Committed Store Buffers CPU Cache Main Memory CPU Cache CPU can continue execution while earlier committed stores are still propagating through memory system Processor can commit other instructions (including loads and stores) while first store is committing to memory Committed store buffer can be combined with speculative store buffer in an out-of-order CPU Local loads can bypass values from buffered stores to same address
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This note was uploaded on 02/19/2008 for the course ECE 4750 taught by Professor Suh during the Fall '07 term at Cornell University (Engineering School).

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ece475-l22 - ECE 475/CS 416 Computer Architecture - Relaxed...

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