ece475-l18 - ECE 475/CS 416 Computer Architecture - Limits...

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1 ECE 475/CS 416 Computer Architecture - Limits to ILP and Multithreading Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements ± Check Lab2 grades ± Reading: Chapter 3
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review ± Dependence analysis algorithms • GCD test ± Techniques to overcome challenges in “classic” VLIW • Compact instruction encoding • Rotating register file • Memory latency register • Predicated instructions • Speculative instructions • Data speculation (reorder loads and stores) ± So far, we have discussed ways to exploit ILP in both HW and SW ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Study on ILP Limits Initial HW Model here; MIPS compilers. Assumptions for ideal/perfect machine to start: 1. Register renaming – infinite virtual registers => all register WAW & WAR hazards are avoided 2. Branch prediction – perfect; no mispredictions 3. Jump prediction – all jumps perfectly predicted (returns, case statements) 2 & 3 ± no control dependencies; perfect speculation & an unbounded buffer of instructions available 4. Memory-address alias analysis – addresses known & a load can be moved before a store provided addresses not equal; 1&4 eliminates all but RAW Also: perfect caches; 1 cycle latency for all instructions (FP *,/); unlimited instructions issued/clock cycle;
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh HW Model Comparison 64KI, 32KD, 1.92MB L2, 36 MB L3 Perfect Cache 2% to 6% misprediction (Tournament Branch Predictor) Perfect Branch Prediction ?? Perfect Memory Alias Analysis 4 Infinite Instructions Issued per clock 200 Infinite Instruction Window Size 88 integer + 88 Fl. Pt. Infinite Renaming Registers Power 5 Model ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Upper Limit to ILP: Ideal Machine Programs Instruction Issues per cycle 0 20 40 60 80 100 120 140 160 gcc espresso li fpppp doducd tomcatv 54.8 62.6 17.9 75.2 118.7 150.1 Integer: 18 - 60 FP: 75 - 150
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh HW Model Comparison Perfect Perfect Perfect Infinite Infinite, 2K, 512, 128, 32 Infinite New Model 64KI, 32KD, 1.92MB L2, 36 MB L3 Perfect Cache 2% to 6% misprediction (Tournament Branch Predictor) Perfect Branch Prediction ?? Perfect Memory Alias Analysis 4 Infinite Instructions Issued per clock 200 Infinite Instruction Window Size 88 integer + 88 Fl. Pt. Infinite Renaming Registers Power 5 Model ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh More Realistic HW: Window Size 55 63 18 75 119 150 36 41 15 61 59 60 10 15 12 49 16 45 10 13 11 35 15 34 88 9 14 9 14 0 20 40 60 80 100 120 140 160 gcc espresso li fpppp doduc tomcatv Instructions Per Clock Inf inite 2048 512 128 32 FP: 9 - 150 Integer: 8 - 63
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5 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh HW Model Comparison Perfect Perfect Perfect vs. 8K Tournament vs.
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This note was uploaded on 02/19/2008 for the course ECE 4750 taught by Professor Suh during the Fall '07 term at Cornell University (Engineering School).

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ece475-l18 - ECE 475/CS 416 Computer Architecture - Limits...

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