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ece475-l19 - ECE 475/CS 416 Computer Architecture...

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1 ECE 475/CS 416 Computer Architecture - Introduction to Multiprocessors Edward Suh C omputer S ystems L aboratory [email protected] ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements ± HW4 is out Due Nov 20th (Tuesday) 5pm ± Reading: Chapter 4 ± Seminar on Friday 12pm (tomorrow) Title: A Vertical Integrated Architecture Design Approach Experiences with Cell processors and GPUs Professor Karu Sankaralingam
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review ± Continue exploiting ILP in the same way is unlikely to scale Power efficiency limits speculation and peak throughput Requires significant breakthrough in HW/SW ± Exploiting more explicit parallelism can be more cost effective Thread Level Parallelism Data Parallelism ± Multithreading / Simultaneous multithreading can better utilize a singe processor by interleaving independent instructions from multiple threads However, slows down individual threads and benefits are rather limited ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Other Factors: Why Multiprocessors? ± Growth in data-intensive applications Data bases, file servers, … ± Growing interest in servers, server perf. ± Increasing desktop perf. less important Outside of graphics ± Improved understanding in how to use multiprocessors effectively Especially server where significant natural TLP ± Advantage of leveraging design investment by replication Rather than unique design
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh What Is a Parallel Computer? ± “A collection of processing elements (PEs) that can communicate and co-operate to solve large problems fast.” (Almási and Gottlieb) ± “A collection of PEs” How many? How powerful? A few powerful cores Many weak cores ± “That can communicate” How do PEs communicate (e.g., shared-memory vs. message-passing, etc.) What interconnect architecture? ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh What Is a Parallel Computer? ± “And co-operate” Synchronization needed to orchestrate communication Sequencing of actions Variety of basic primitives: Test&Set, Fetch&Add, etc. Synchronization constructs: Locks, Flags, Barriers, etc. Granularity of parallelism? Typically grain size ± ² parallelism ³ , communication ³ , overhead ³ Intuitively: No. instructions per thread Program level 1e6+ inst. Task level 1e3-1e6 inst. Loop level 10-1e3 inst. ILP 2-15 inst.
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Flynn s Taxonomy ± Flynn classified by data and control streams in 1966 ± SIMD ± Data Level Parallelism ± MIMD ± Thread Level Parallelism ± MIMD popular because Flexible: N programs or 1 multithreaded program Cost effective: same MPU in desktop & MIMD Multiple Instruction Multiple Data MIMD (Clusters, SMP servers) Multiple Instruction Single Data (MISD) (????) Single Instruction Multiple Data SIMD (single PC: Vector, CM-2) Single Instruction Single Data (SISD)
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