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ece475-l11

ece475-l11 - 1 ECE 475/CS 416 Computer Architecture Virtual...

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Unformatted text preview: 1 ECE 475/CS 416 Computer Architecture- Virtual Memory Edward Suh C omputer S ystems L aboratory [email protected] ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements ¡ Homework 3 ¡ Prelim conflict should be reported by the end of this week 2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review ¡ Improving cache performance • Reduce hit time • Reduce miss rate • Reduce miss penalty ¡ There are other factors that are intimately connected with cache design • Virtual memory and associated address translation • Multiprocessor and associated memory model issues ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Names for Memory Locations ¡ Machine language address • as specified in machine code ¡ Virtual address • ISA specifies translation of machine code address into virtual address of program variable (sometime called effective address) ¡ Physical address ¡ operating system specifies mapping of virtual address into name for a physical memory location physical address virtual address machine language address Address Mapping ISA Physical Memory (DRAM) 3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Absolute Addresses ¡ Only one program ran at a time, with unrestricted access to entire machine (RAM + I/O devices) ¡ Addresses in a program depended upon where the program was to be loaded in memory ¡ But it was more convenient for programmers to write location- independent subroutines virtual address = physical memory address EDSAC, early 50’s How could location independence be achieved? Linker and/or loader modify addresses of subroutines and callers when building a program memory image ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Dynamic Address Translation Motivation In the early machines, I/O operations were slow and each word transferred involved the CPU Higher throughput if CPU and I/O of 2 or more programs were overlapped. How? ¡ multiprogramming Location-independent programs Programming and storage management ease ¡ need for a base register Protection Independent programs should not affect each other inadvertently ¡ need for a bound register prog1 prog2 Physical Memory 4 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Simple Base and Bound Translation Load X Program Address Space Bound Register ¡ Bounds Violation? Main Memory current segment Base Register + Physical Address Effective Address Base and bounds registers are visible/accessible only when processor is running in the supervisor mode Base Physical Address Segment Length ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Separate Areas for Program and Data What is an advantage of this separation?...
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ece475-l11 - 1 ECE 475/CS 416 Computer Architecture Virtual...

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