ece475-l13 - ECE 475/CS 416 Computer Architecture -...

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1 ECE 475/CS 416 Computer Architecture - Speculative Execution I Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements ± Prelim will be 7:30-9:30pm on Oct 11th (PH101) ± No class next week • Tuesday: fall break, Thursday: exam ± No office hours on Monday and Tuesday
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review ± Branch penalties limit performance of advanced processors • Average basic block size is 4-12 instructions • Gets worse when (a) issue ± , (b) pipeline depth ± ± Dynamic branch prediction techniques can be very effective: ~97% • Exploits temporal and spatial correlations • BTB for target address prediction ± Fetch from predicted path ahead of branch resolution ± Cannot afford to fetch and wait – must execute speculatively ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Speculative Execution ± Instructions from predicted path allowed to execute (enter EX stage) ± Powerful combination: Speculation+Dynamic Scheduling • Aggressive cross-BB dynamic scheduling ± Used in virtually all modern microprocessors • PowerPC G4, MIPS R12000, Pentium 4, AMD Athlon, Alpha 21264 ± Must provide recovery mechanism in case of misprediction • Speculative instructions may not commit state changes • Speculative results must be still be provided to others
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Tomasulo-based FPU ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Three Steps to Instruction Execution ± Step 1: Issue • if reservation station available (structural), then • rename operands, send instruction to reservation station ± Step 2: Execution • if operand(s) not available, monitor CDB (snoop) • inform control logic at completion ± Step 3: Write result • broadcast result via CDB • if no WAW hazard, update register
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ece475-l13 - ECE 475/CS 416 Computer Architecture -...

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