ece475-l14 - ECE 475/CS 416 Computer Architecture...

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1 ECE 475/CS 416 Computer Architecture - Speculative Execution II Edward Suh C omputer S ystems L aboratory [email protected] ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Announcements ± No class on Thursday No office hour 11-12 ± HW2 re-grade request till 23rd
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review: ROB ± Reservation stations (RS): buffer op and operands once issued until executed track assigned ROB entry ± ROB provide renaming mechanism (tag results with ROB entry instead of RS) hold instruction’s relevant state from issue to commit, including result if any ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Speculative Execution with IW Basic Operation: • Enter op and tag or data (if known) for each source • Replace tag with data as it becomes available • Issue instruction when all sources are available • Save dest data when operation finishes • Commit saved dest data when instruction commits Register File < t, result > Ins# use exec op p1 src1 p2 src2 pd dest d ata Rename Table R1 R2 tag valid bit t 1 t 2 . . t n 0 X X add X 1 X 2 X R4 4 8 X ld X 256 R3 R1 1 R2 2 R3 3 : Next to commit Next available R3 R4 Load Unit FU FU FU Store Unit Commit t i t j 0 : : t 2 t 1 0 1 1
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Unified Physical Register File (MIPS R10K, Alpha 21264, Pentium 4) • One regfile for both committed and speculative values (no data in ROB/IW) • During decode, instruction result allocated new physical register, source regs translated to physical regs through rename table • Instruction reads data from regfile at start of execute (no data in RS/IW) • Write-back updates reg. busy bits on instructions in ROB/IW (assoc. search) Rename Table r 1 t i r 2 t j FU Store Unit < t, result > FU Load Unit FU t 1 t 2 . t n Reg File (ROB/IW not shown) ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Lifetime of Physical Registers ± Physical regfile holds both committed and speculative values ld r1, (r3) add r3, r1, #4 sub r6, r7, r9 add r3, r3, r6 ld r6, (r1) add r6, r6, r3 st r6, (r1) ld r6, (r11) ld P1, (P x ) add P2, P1, #4 sub P3, P y , P z add P4, P2, P3 ld P5, (P1) add P6, P5, P4 st P6, (P1) ld P7, (P w ) Rename When can we reuse a physical register? When next write of same architectural register commits
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Physical Register Management op p1 PR1 p2 PR2 ex use Rd PRd LPRd <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 R5 P5 R6 P6 R7 R0 P8 R1 R2 P7 R3 R4 ROB Rename Table Physical Regs Free List ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) p p p P0
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