ece475-l8 - ECE 475/CS 416 Computer Architecture - Dynamic...

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1 ECE 475/CS 416 Computer Architecture - Dynamic Scheduling II Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2006 Prof. Suh Scoreboard Review ± Step 1: issue • if FU available (structural), and • if no earlier instruction writes to same destination (WAW), then • send instruction to FU ± Step 2: read operands (a.k.a. dispatch ) • if no operand pending update (RAW), then • instruct FU to read operands and start execution ± Step 3: execution • inform scoreboard at completion ± Step 4: write result (a.k.a. retire ) • if WAR hazard possible, stall at WB stage
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2 ECE 475/CS 416 — Computer Architecture, Fall 2006 Prof. Suh Parts of Scoreboard ± Instruction Status – in which of the four steps each instruction is ± FU Status – is FU available? Busy – FU is busy Op – operation to be performed F i , F j , F k – Destination and source registers Q j , Q k – FUs producing F j , F k R j , R k – Operand-ready flags; reset after operands are read ± Register Status – is a register (Reg) up-to-date? Result[Reg] which FU will write Reg ECE 475/CS 416 — Computer Architecture, Fall 2006 Prof. Suh Scoreboard Details ± Issue • Wait till no structural (not Busy[FU]) and WAW (not Result[D]) hazard • Busy[FU] = yes; Op[FU] = op; Fi[FU] = D; Fj[FU] = S1; Fk[FU] = S2; Qj = Result[S1]; Qk = Result[S2]; Rj = not Qj; Rk = not Qk; Result[D] = FU ± Read operands • Wait till no RAW hazard: Rj and Rk • Rj = No; Rk = No; Qj = 0; Qk = 0 ± Execution ± Write result • Wait till no WAR hazard: for all other FUs, sources (Fj, Fk) that are in the register file (Rj, Rk == yes) do not match the register (Fi[FU]) to overwite • Rj[f], Rk[f] = yes if Qj[f], Qk[f] == FU; Result[Fi[FU]] = 0; Busy[FU] = No;
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3 ECE 475/CS 416 — Computer Architecture, Fall 2006 Prof. Suh Limitations: an example latency 1 LD F2, 34(R2) 1 2 LD F4, 45(R3) long 3 MULTD F6, F4 ,F 2 3 4 SUBD F8, F2, F2 1 5 DIVD F4 2 8 4 6 ADDD F10, F6, F4 1 In-order: 1 (2,1 ) . . . . . . 2 3 4 4 3 5 . . . 5 6 6 1 2 3 4 5 6 Out-of-order: 1 (2,1 ) 4 4 . . . . 2 3 . . 3 5 . . . 5 6 6 Out-of-order execution did not allow any significant improvement! ECE 475/CS 416 — Computer Architecture, Fall 2006 Prof. Suh How many Instructions can be in the Pipeline? Which features of an ISA limit the number of instructions in the pipeline? Which features of a program limit the number of instructions in the pipeline? Out-of-order dispatch by itself does not provide any significant performance improvement !
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4 ECE 475/CS 416 — Computer Architecture, Fall 2006 Prof. Suh Instruction-level Parallelism via Renaming latency 1 LD F2, 34(R2) 1 2 LD F4, 45(R3) long 3 MULTD F6, F4, F2 3 4 SUBD F8, F2, F2 1 5 DIVD F4’ ,F 2 , F 8 4 6 ADDD F10, F6, F4’ 1 In-order: 1 (2,1 ) . . . . . . 2 3 4 4 3 5 . . . 5 6 6 Out-of-order: 1 (2,1 ) 4 4 5 . . . 2 (3,5 ) 3 6 6 1 2 3 4 5 6 X Any name dependence can be eliminated by renaming. (renaming ± additional storage) ECE 475/CS 416 — Computer Architecture, Fall 2006 Prof. Suh Dynamic Scheduling by Tomasulo’s ± Developed for IBM 360/91 three years after CDC 6600 ± Goal was high performance without compiler help • only four floating-point registers • wanted portability of code ±
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This note was uploaded on 02/19/2008 for the course ECE 4750 taught by Professor Suh during the Fall '07 term at Cornell University (Engineering School).

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ece475-l8 - ECE 475/CS 416 Computer Architecture - Dynamic...

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