ece475-l9 - ECE 475/CS 416 Computer Architecture - Caches...

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1 ECE 475/CS 416 Computer Architecture - Caches and Memory I Edward Suh C omputer S ystems L aboratory suh@csl.cornell.edu ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Review ± Dynamic scheduling tries to reduce pipeline stalls and bubbles by exploiting ILP • Out-of-order execution • Register renaming ± There are remaining questions • How to handle control dependence? • How to handle exceptions? ± We will come back to these issues
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Overview ± Memory hierarchy basics • memory technologies • principle of locality ± Caches • concepts: block, write policy, associativity, block replacement • performance estimation: average memory access time • performance techniques – reduce miss rate – reduce miss penalty – reduce hit time ± Virtual memory • paging, dynamic address translation, TLB ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh CPU-Memory Bottleneck ± Performance of high-speed computers is usually limited by memory • Latency (time for a single access) – Memory access time >> Processor cycle time • Bandwidth (number of accesses per unit time) – if fraction m of instructions access memory, 1+m memory references / instruction CPI = 1 requires 1+m memory refs / cycle Memory CPU
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Memory in 60s DEC PDP-8/E Board, 4K words x 12 bits, (1968) ± Robust, non-volatile storage ± Used on space shuttle computers until recently ± Cores threaded onto wires by hand (25 billion a year at peak production) ± Core access time ~ 1 μ s ± Core memory was first large scale reliable main memory • invented by Forrester in late 40s at MIT for Whirlwind project ± Bits stored as magnetization polarity on small ferrite cores threaded onto 2 dimensional grid of wires ± Coincident current pulses on X and Y wires would write cell and also sense original state (destructive reads) ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Semiconductor Memory, DRAM ± Semiconductor memory began to be competitive in early 1970s • Intel formed to exploit market for semiconductor memory ± First commercial DRAM was Intel 1103 • 1Kbit of storage on single chip • charge on a capacitor used to hold value ± Semiconductor memory quickly replaced core in 1970s
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh One Transistor Dynamic RAM TiN top electrode (V REF ) Ta 2 O 5 dielectric W bottom electrode poly word line access transistor 1-T DRAM Cell word bit access transistor Storage capacitor (FET gate, trench, stack) V REF ECE 475/CS 416 — Computer Architecture, Fall 2007 Prof. Suh Technology Trends Revisited 2 ± /10yr 4 ± /2yr Disk 2 ± /15yr 4 ± /3yr DRAM 2 ± /3yr 4 ± /3yr Logic Speed Capacity 120ns 64Mb 1995 145ns 16Mb 1992 165ns 4Mb 1989 190ns 1Mb 1986 220ns 256Kb 1983 250ns 64Kb 1980 Cycle Time Size Year DRAM 1000 ± capacity 2 speed
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This note was uploaded on 02/19/2008 for the course ECE 4750 taught by Professor Suh during the Fall '07 term at Cornell University (Engineering School).

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ece475-l9 - ECE 475/CS 416 Computer Architecture - Caches...

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