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hw17_SLN

# hw17_SLN - ECE 211 HW 17 SOLUTIONS p 1/12...

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ECE 211 HW 17 SOLUTIONS p 1/12 //home/vdimitrov/8850/f2fcbd05ff9049a1b19083ae72c6cdcb93ce2454.doc HW 17 SOLUTIONS 1. For the state transition diagram and waveforms shown, neatly construct the Z waveform. The circuit contains rising edge-triggered flip-flops and is initially in the 00 state. Solution:

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ECE 211 HW 17 SOLUTIONS p 2/12 2. Design the clocked circuit whose State Transition Diagram is given in Problem 1. The circuit input and output are active-Low. Use logic gates (any types) in your realization. Solution: Circuit: Truth Table for Next State: Q1 Q0 X Q1+ Q0+ 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 1
ECE 211 HW 17 SOLUTIONS p 3/12 ( 2. ) Maps and Expressions: Truth Table for Output: Q1 Q0 Z 0 0 0 0 1 0 1 0 0 1 1 1 Z = Q1 Q0 Circuit: (next page)

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ECE 211 HW 17 SOLUTIONS p 4/12 ( 2. ) Circuit:
ECE 211 HW 17 SOLUTIONS p 5/12 3. For the state transition diagram and waveforms shown, carefully construct the Z waveform. The circuit contains rising edge-triggered flip-flops and is initially in the 00 state. Solution:

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ECE 211 HW 17 SOLUTIONS p 6/12 4. Design the clocked circuit whose State Transition Diagram is given in Problem 3. The circuit input and output are active-Low. Use logic gates (any types) in your realization.
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