hw04SLN - Between Failure. (Ans: 0.5 ms) (b) If a...

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ECE 212 HW Set 4 SLN p 1 of 3 Homework Set 4 Solution 1. Carefully complete the timing diagram below to show: the DR_Flag signal the DR_Rst signal the system state. In this diagram, the system clock is fast relative to Strobe. Assume that the DR_Flag signal as shown meets the circuit input window specification. Solution: (Next page)
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ECE 212 HW Set 4 SLN p 2 of 3 (1. Solution) NOTE: When the controller returns to state A, the Strobe pulse is still present but the DR_Flag is be 0. The DR_Flag will go to 1 again only when another rising edge occurs on the Strobe signal.
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ECE 212 HW Set 4 SLN p 3 of 3 2. A digital system has the parameters: Clock frequency: f CLK = 200 MHz Input window: W = 1 ns Input data rate: f d = 10 KHz Flip-flops: K 1 = 10 – 10 s K 2 = 7.87 ns – 1 The system latches the Strobe input. (a) If no synchronizing flip-flop is used between the Strobe latch and the system, calculate the Mean Time
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Unformatted text preview: Between Failure. (Ans: 0.5 ms) (b) If a synchronizing flip-flop is used, calculate the Mean Time Between Failure. Be careful with the units. (Ans: 7440 years, to 3 significant figures.) Solution: (a) Check the requriement for the equation: f d W = 10 KHz x 1 ns = ( 10 4 /s) ( 10 9 s ) = 10 5 < < 1 MTBF = 1 / ( f CLK f d W ) = 1 / [ (200 x 10 6 /s) ( 10 4 /s) ( 10 9 s ) ] = 1/ 2000 = 0.5 ms (b) MTBF = e ( K2 To ) / ( f CLK f d K 1 ) To = ( 1/ f CLK ) W = ( 1/200 MHz) 1 ns = 5 ns 1 ns = 4 ns = e ( 7.87 /ns) ( 4 ns ) / [ (200 x 10 6 /s) ( 10 4 /s) ( 10 10 s ) ] = 2.35 x 10 11 s = ( 2.35 x 10 11 s ) ( 1 m / 60 s ) ( 1 hr / 60 m ) ( 1 day / 24 hr ) ( 1 yr / 365 days ) = 7443 yrs...
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This homework help was uploaded on 04/17/2008 for the course ECE 212 taught by Professor Greco during the Spring '08 term at Lafayette.

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hw04SLN - Between Failure. (Ans: 0.5 ms) (b) If a...

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