hw02SLN - ECE 212 HW Set 2 Solutions p 1 of 11

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ECE 212 HW Set 2 Solutions p 1 of 11 //home/vdimitrov/25650/a500b39054139c2ff3449cffb70d81abb7a2e6d9.doc ECE 212 Homework Set 2 – SOLUTIONS 1. (ECE 211 material) This problem refers to the D flip-flop with Clock Enable input. The input-output table appears below. You will realize this device using an ordinary D flip-flop plus combinational logic, as shown below. (a) From the table, write a logic expression for Q+ in terms of CE, D and Q. (b) Realize your expression with a logic gate circuit. The inputs and outputs are all active-High. (c) Do you recognize this combinational circuit? CE D Q+ 0 Q 1 0 0 1 1 1 Solution: (a) Q+ = ( CE ) ' · Q + (CE ) · D (b) (b) The circuit is a 2-to-1 line multiplexer. The switching is performed by the CE input, with data inputs Q, D:
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ECE 212 HW Set 2 Solutions p 2 of 11 2. (ECE 211 material) A 4-bit shift register is a clocked circuit with four flip-flops, the clock input and the input S (for Shift). When S = 1, the flip-flop values move one place; when S = 0, the flip-flop values do not change. This behavior is described in the table below (Q3 is the current state of flip-flop 3; Q3+ is the new state). S Q3+ Q2+ Q1+ Q0+ 0 Q3 Q2 Q1 Q0 1 Q2 Q1 Q0 0 (a) Write a logic expression for Q3+. (b) Write a logic expression for Q2+. (c) Write a logic expression for Q1+. (d) Write a logic expression for Q0+. Solution: (a) Q3+ = S’ & Q3 + S (b) Q2+ = S’ & Q2 + S (c) Q1+ = S’ & Q1 + S (d) Q0+ = S’ & Q0 + S & 0 = S’ & Q0
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ECE 212 HW Set 2 Solutions p 3 of 11 3. For the three registers shown, neatly complete the timing diagram to show the contents of the registers for two clock pulses. All three registers have their Clock Enable inputs connected together to the Load signal. The inital register contents are shown in the timing diagram, along with the X and Load signals. Solution: At the second clock rising edge, Load = 1 and all three registers are loaded. Register A receives the value of X, register B receives the value in A, register C receives the value in B.
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ECE 212 HW Set 2 Solutions p 4 of 11 4. This question refers to the State Transition Diagram developed in lecture. Can we remove state S4, and perform the (A < B ) test in state S3? Please explain your answer.
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hw02SLN - ECE 212 HW Set 2 Solutions p 1 of 11

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