ece475-l1 - ECE 475/CS 416 Computer Architecture...

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1 ECE 475/CS 416 Computer Architecture - Introduction Edward Suh C omputer S ystems L aboratory [email protected] ECE 475/CS 416 — Computer Architecture, Fall 2007 Suh ECE 475/CS 416 Requirements ± Prerequisites ENGRD 230 or equivalent, and ECE 314 or equivalent logic design, FSM design basic computer organization ± Assets passion for computer hardware prior exposure to Unix and/or Verilog ability to work nonstop for extended periods of time ± You should not take this course if any of these apply you do not meet the prerequisites your schedule and/or lifestyle won’t fit a(nother) high-workload course
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2 ECE 475/CS 416 — Computer Architecture, Fall 2007 Suh Staff ± Instructor: Edward Suh, 338 Rhodes, office hours TuTh 11am-Noon ± Teaching assistants: (office hours M-Th 7-9pm & Th 5-7pm, PH329) Muhammad Adnan Danny Deng Morgan Jones Mitchell Kotler Janani Mukundan ± Official newsgroup: cornell.class.ece475 look up your answer first ; if not there, post your question ± If you must, use the staff’s email: [email protected] but we may post your question (and our answer) in the newsgroup ECE 475/CS 416 — Computer Architecture, Fall 2007 Suh Course Web Site ± Including, but not limited to: official announcements (e.g. handouts, date changes, etc.) clarifications, errata online resources FAQ ± All assignments handled through CMS
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3 ECE 475/CS 416 — Computer Architecture, Fall 2007 Suh Grading ± Grade distribution: homework 10% midterm 15% (Oct. 11, Phillips 101) final 35% (TBA) Verilog projects 40% (5% + 5% + 10% + 20%) good citizenship, at my discretion (half grade, e.g. B+ to A-) ± Exams are open book, open notes they won’t help much ± Late policy: 1min late = not submitted = zero (I’m not kidding) but you have one lifeline on one assignment – 24 hours all parties involved must have lifeline available assignments: ECE 475/CS 416 — Computer Architecture, Fall 2007 Suh Labs ± Verilog design projects incredibly useful language to know — industry loves Verilog projects done in teams of two ± Expand on a basic MIPS R3000 processor Lab 0: Welcome to Verilog (not graded ) Lab 1: Get used to processor model, fix bugs, add instructions Lab 2: Pipeline model, add forwarding logic Lab 3: Add caches and cache controller Lab 4 Final Lab (next)
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4 ECE 475/CS 416 — Computer Architecture, Fall 2007 Suh Final Lab ± Superscalar (dual-issue) pipeline ± Design a processor extension of your choosing branch prediction dynamic scheduling hardware prefetchers speculative loads multiple-level caches instruction set extensions [your idea here] ± Project report required ECE 475/CS 416 — Computer Architecture, Fall 2007 Suh What Do I Need to Know?
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