ENGR 2720 Chapter 05

ENGR 2720 Chapter 05 - Chapter 5 Introduction to VHDL 1...

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1 Chapter 5 Introduction to VHDL
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2 Chapter 5 Homework 5.1, 5.3, 5.5, 5.7, 5.17, 5.25
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3 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits. VHDL (VHSIC V ery H igh S peed I ntegrated C ircuit H ardware D escription L anguage) is the industry-standard language used for programming PLDs.
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4 VHDL History Developed by defense contractors as a standard for programming circuits. Currently defined by IEEE Standard 1076- 1993. Related standard for certain data types is IEEE Standard 1164-1993.
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5 VHDL – 1 Used to describe the structure or behavior of hardware. Describes how the hardware should operate (modeling). Describes how how the hardware should be built (synthesis).
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6 VHDL – 2 In VHDL the designer enters text according to the syntax of the language. Syntax: The rules of construction, or “grammar”, of a programming language.
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7 Entity and Architecture Two basic constructs required for all VHDL code. The entity declaration describes the inputs and outputs. The architecture body defines the relationships between the inputs and outputs.
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8 VHDL Entity Defines the external aspects of the function. Each input or output is a port . The type of port is defined by mode .
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9 AC BC AB Y + + = VHDL Entity
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10 VHDL Entity Declaration ENTITY majority_vote IS PORT( a, b, c: IN BIT; y : OUT BIT); END majority_vote;
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11 VHDL Architecture Body ARCHITECTURE maj_vote OF majority vote IS BEGIN y <= (a and b) or (b and c) or (a and c); END maj_vote;
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12 Port Types IN refers to a port used only for input. OUT refers to a port used only for output. BIT refers to the port type. A port designated as type BIT can have a value of either ‘0’ or ‘ 1 ’ .
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13 Boolean Operators in VHDL AND, OR, NOT, NAND, NOR, XOR, and XNOR are represented as written. VHDL has no order of precedence for Boolean operators. Expressions must be written explicitly with parentheses.
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14 Boolean Operators Example Y <= (a and(not b)) or ((not a) and b and (not c)); Y <= not((a and b) or ((not a) and (not c)) or d); C B A B A Y + = D C A AB Y + + =
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15 Signal Concurrency Concurrent means simultaneous. The statements in an architecture body are
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This note was uploaded on 04/15/2008 for the course ETEC ENGR 2720 taught by Professor Grubbs during the Spring '08 term at North Texas.

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ENGR 2720 Chapter 05 - Chapter 5 Introduction to VHDL 1...

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