Timing Analysis & Optimization - EE271 Thuy T Le SJSU EE EE271 Advanced Digital System Design Synthesis Timing Analysis and Optimization Lets take 4

Timing Analysis & Optimization - EE271 Thuy T Le SJSU EE...

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EE271 @ Thuy T. Le SJSU - EE Chapter 3: Timing Analysis and Optimization 1 EE271 Advanced Digital System Design & Synthesis Timing Analysis and Optimization Chapter 3: Timing Analysis and Optimization 1 Let’s take 4 lectures for this topic Synchronous, Asynchronous, and Self-timed Functions of clock in synchronous design Acts as completion signal Ensures the correct ordering of events Truly asynchronous design Completion is ensured by careful timing analysis Ordering of events is implicit in logic Self-timed design (that we mostly call asynchronous) Completion ensured by completion signal Ordering imposed by handshaking protocol Chapter 3: Timing Analysis and Optimization 2
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EE271 @ Thuy T. Le SJSU - EE Chapter 3: Timing Analysis and Optimization 2 Time Delay of Flip-flop (register) and Latch (transparent) Chapter 3: Timing Analysis and Optimization 3 D Clk Q Clk D Q D Clk Q Clk D Q Flip-flop Latch Clk D Q t C2Q Clk D Q t C2Q t D2Q Synchronous Timing Chapter 3: Timing Analysis and Optimization 4 D Q Clock t C2Q t hold T clock t S Flip-flop/Register t C2Q D Q Clock t C2Q t hold t S t D2Q T clock Latch t C2Q
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