ENGR 2720 Chapter 06

ENGR 2720 Chapter 06 - Chapter 6 Combinational Logic...

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1 Chapter 6 Combinational Logic Functions

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2 Chapter 6 Homework 6.1, 6.5, 6.7a&b, 6.15, 6.19a&b, 6.21, 6.23, 6.29, 6.45
3 Basic Decoder Decoder: A digital circuit designed to detect the presence of a particular digital state. Can have one output or multiple outputs. Example: 2-Input NAND Gate detects the presence of ‘11’ on the inputs to generate a ‘0’ output.

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4 Single-Gate Decoders Uses single gates (AND/NAND) and some Inverters. Example: 4-Input AND detects ‘1111’ on the inputs to generate a ‘1’ output. • Inputs are labeled D 3 , D 2 , D 1 , and D 0 , with D 3 the MSB (most significant bit) and D 0 the LSB (least significant bit).
5 Single-Gate Decoders D 3 D 3 D 0 D 2 D 2 D 1 D 1 D 0 Y = (D 3 D 0 )’ D 2 D 1 Y = D 3 D 0 D 2 D 1

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6 Single-Gate Examples If the inputs to a 4-Input NAND are given as , then the NAND detects the code 0001. The output is a 0 when the code 0001 is detected. This type of decoder is used in Address Decoding for a PC System Board. 4 3 2 1 , D D , D , D
7 Multiple Output Decoders Decoder circuit with n inputs can activate m = 2 n load circuits. Called a n -line-to- m -line decoder, such as a 2-to-4 or a 3-to-8 decoder. Usually has an active low enable that enables the decoder outputs. G

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8 2-to-4 Decoder
9 3-to-8 Decoder

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10 Truth Table for a 3-to-8 Decoder 1 1 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X 1 Y Y Y Y Y Y Y Y D D D G 7 6 5 4 3 2 1 0 0 1 2
11 74138 3-to-8 Decoder

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12 74138 3-to-8 Decoder
13 Simulation Simulation: The verification of a digital design using a timing diagram before programming the design in a CPLD. Used to check the Output Response of a design to an Input Stimulus using a timing diagram.

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14 Simulation
15 VHDL Binary Decoder Use select signal assignment statements constructs or conditional signal assignment statements constructs.

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16 2-to-4 Decoder VHDL Entity Using a select signal assignment statement: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode3 IS PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode3;
17 Selected Signal Entity In the previous slide, the Entity used a STD LOGIC Array for Inputs and Outputs. The Y : OUT STD_LOGIC_VECTOR(3 downto 0) is equal to Y 3 , Y 2 , Y 1 , Y 0 . The STD_LOGIC Data Type is similar to BIT but has added state values such as Z, X, H, and L instead of just 0 and 1.

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18 Selected Signal Assignments Uses a VHDL Architecture construct called WITH SELECT. Format is: WITH (signal input(s)) SELECT. Signal input states are used to define the output state changes.
19 2-to-4 Decoder VHDL Architecture ARCHITECTURE decoder OF decode3 IS BEGIN WITH d SELECT y <= “0001” WHEN “00”, “0010 WHEN “01”, “0100” WHEN “10”, “1000” WHEN “11”, “0000” WHEN others; END decoder;

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20 Decoder Architecture The decoder Architecture used a SELECT to evaluate d to determine the Output
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This note was uploaded on 04/15/2008 for the course ETEC ENGR 2720 taught by Professor Grubbs during the Spring '08 term at North Texas.

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ENGR 2720 Chapter 06 - Chapter 6 Combinational Logic...

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