Lec10 - ECE 212 Digital Circuits II Wednesday, 27 February...

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1 ECE 212 Digital Circuits II Wednesday, 27 February 2008 ± HW Set 10: Problem 1 No presenter. Problem 2 Aaron L. Problem 3 Connor M. Problem 4 Chris N. Problem 5 Peter P. Lecture 10 Goals ± To review the hexadecimal number system. ± To introduce a programmable stack calculator.
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2 FPGA Design Entry ± Schematic ± ABEL ± State Transition Diagram ± Verilog ± VHDL Very high-speed IC Hardware Description Language FPGA Design Entry ± Schematic ± ABEL ± State Transition Diagram Verilog is also used in: ECE 313 Computer Organization ECE 491 Senior Design I VLSI Elective ECE 211, 212 ± Verilog ± VHDL Very high-speed IC Hardware Description Language
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3 Verilog Description Synthesizable. A behaviorial description: NO explicit data path; NO explicit control circuit. Time for any operation: ONE clock period. Synthesis Result Stack Registers Combinational Circuit NO control circuit.
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Hexadecimal Numbers ± Hexadecimal: Base-16 Number System Place values are powers of 16: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F There are sixteen digits: . . . 16 2 16 1 16 0 . . . 256 16 1 Hexadecimal and Binary N = b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 (binary) Let N be expressed in 12-bit binary: The value of N is N = b 11 × 2 11 + b 10 × 2 10 + b 9 × 2 9 + b 8 × 2 8 +b 7 × 2 7 + b 6 × 2 6 + b 5 × 2 5 + b 4 × 2 4 +b 3 × 2 3 + b 2 × 2 2 + b 1 × 2 1 + b 0 × 2 0 N = 2 8 × ( b 11 × 2 3 + b 10 × 2 2 + b 9 × 2 1 + b 8 × 2 0 ) +2 4 × ( b 7 × 2 3 + b 6 × 2 2 + b 5 × 2 1 + b 4 × 2 0 ) + 2 0 × (b 3 × 2 3 + b 2 × 2 2 + b 1 × 2 1 + b 0 × 2 0 ) N = 16 2 × ( b 11 × 2 3 + b 10 × 2 2 + b 9 × 2 1 + b 8 × 2 0 ) + 16 1 × ( b 7 × 2 3 + b 6 × 2 2 + b 5 × 2 1 + b 4 × 2 0 ) + 16 0 × (b 3 × 2 3 + b 2 × 2 2 + b 1 × 2 1 + b 0 × 2 0 ) h2 h1 h0 Hexa-
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This note was uploaded on 04/17/2008 for the course ECE 212 taught by Professor Greco during the Spring '08 term at Lafayette.

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Lec10 - ECE 212 Digital Circuits II Wednesday, 27 February...

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