Lec03 - ECE 212 Digital Circuits II Monday, 4 February 2008...

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1 ECE 212 Digital Circuits II Monday, 4 February 2008 ± HW Set 3: Problem 1 No presenter. Problem 2 Steve H. Problem 3 Bill H. Problem 4 Andrew J. Problem 5 Mark K. Problem 6 No presenter (lab exercise) Problem 7 Aaron L. Quiz Problem 1 S2 S3 0101 ZMux = X ZMux = A’ 0011 0011 0101 ZMux = X Register A contents cannot change until end of S2.

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2 Lecture 3 Goals ± To understand how to multiply binary numbers. ± To outline the design of a system to perform multiplication of two 4-bit (unsigned) numbers . Algorithm A: Repeated addition. Algorithm B: Add, shift. Reset Multiplier Overview clock InDR Rdy 4 4 X[3:0] Y[3:0] Z[ ?? : 0] Bus Size ?? Unsigned Data Rdy: Z is ready; System is ready for new inputs. Largest possible product: (1111) 2 x (1111) 2 = = (225) 10 (15) 10 x (15) 10 = (11100001) 2
3 Multiplier Overview 4 4 clock InDR Rdy X[3:0] Y[3:0] Z[ 7 : 0] Largest possible product: (1111) 2 x (1111) 2 = = (225) 10 Unsigned Data We need 8 bits. Rdy: Z is ready; System is ready for new inputs. (15) 10 x (15) 10 = (11100001) 2 Reset Algorithm A: Multiplication is repeated addition. ± X × Y means "Add X Y times." ± Data Path: Adder Counter

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4 3. while (Counter 0) { } Data Path, Algorithm Product Register Add Register Counter Algorithm A: 2. X Register; LdX 1. Wait for InDR; Rdy = 1; X[3:0] Y[3:0] Z[7:0] LdP ResP
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This note was uploaded on 04/17/2008 for the course ECE 212 taught by Professor Greco during the Spring '08 term at Lafayette.

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Lec03 - ECE 212 Digital Circuits II Monday, 4 February 2008...

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