Lec08 - ECE 212 Digital Circuits II Wednesday 20 February 2008 HW Set 8 Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Rhodes B Andy B Alyssa B

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1 ECE 212 Digital Circuits II Wednesday, 20 February 2008 ± HW Set 8: Problem 1 Rhodes B. Problem 2 Andy B. Problem 3 Alyssa B. Problem 4 Hank B. Problem 5 Chris D. HW Set 7, Problem 5(b) Inputs: X[3:0], Y[3:0] 4-bit binary data. c[2:0] Control inputs. Output:Z[3:0] 4-bit binary data. Use a bus.
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2 Today's Goals To undestand some problems that can (and will) cause trouble in a digital design. System clock Clock skew. Maximum clock frequency. Output loading. ANALOG circuit analysis !! Transients. Synchronous control signal vs. asynchronous control signal. Today's Goals System clock Clock skew. Maximum clock frequency. Output loading. ANALOG circuit analysis !! Transients. Synchronous control signal vs. asynchronous control signal. ± To undestand some problems that can (and will) cause trouble in a digital design.
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3 Q1 Q0 = clock 00 D1 Q0 Q1 D0 Clocked Circuit Timing 11 00 11 10 01 Q1Q0 Q1 Q0 D1 D0 Both flip-flops respond at the same time. Q1 Q0 Clock Skew 01 Delay Incorrect state transition! The circuit flip-flops do NOT respond at the same time. Q1 clock Q0 clock state Q1 Q0 = Q0 clock 00 Q0 Q1 D1 D0 01 Q1 clock 00 11 10 01 Q1Q0
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4 Another View: Unwrap the Circuit >> clock Q0 clock Q1 Q0 D1 t pCQ t comb Q1 clock Skew Requirement: Skew < ( t pCQ + t comb ) The Q1 clock edge must arrive BEFORE D1 changes. Q1 Q0 Delay Q1 clock Q0 clock Case Study (1/7) 9 modulo-ten counters. Clock Lots of flip-flops! (36)
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5 Case Study (2/7) Routed design.
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This note was uploaded on 04/17/2008 for the course ECE 212 taught by Professor Greco during the Spring '08 term at Lafayette.

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Lec08 - ECE 212 Digital Circuits II Wednesday 20 February 2008 HW Set 8 Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Rhodes B Andy B Alyssa B

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