Lec04 - ECE 212 Digital Circuits II Wednesday 6 February...

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1 ECE 212 Digital Circuits II Wednesday, 6 February 2008 HW Set 4 Problem 1 Chris N. Problem 2 Peter P. Lab Notebooks Leave in lab after every lab period. Options: A bound notebook. A Word file on the lab computer. Person making the entry alternates each week.
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2 Lecture 4 Goals To understand strobed data and how to acquire it. To understand how to use Verilog for: A structural description. A test fixture. Strobed Data Data Source Data Data is momentarily availabe. Strobe indicates when the data lines hold valid data. Strobe Valid Data Data Strobe Digital System clock Asynchronous Systems
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3 Data Reception Approach I: Monitor the Strobe signal. Valid Data Data Strobe Strobe ' Strobe System Control Circuit: R A Data Source Data Strobe Digital System clock Possible Problem 1 Strobe is examined at every rising edge of the clock. Valid Data Data Strobe Strobe ' Strobe R A System clock is relatively slow. clock Problem: Solution: The system misses the data. Increase the clock frequency. The system has a maximum clock frequency.
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4 Possible Problem 2 Problem: Strobe ' Strobe R A System clock is relatively fast. The system uses the same data again. Solutions: Option 1. Wait for the end of the Strobe pulse. clock Valid Data Data Strobe state Duplicate Data R R R R R R A B . . . R A Option 2. (Next slide) Solution 2 DR_Flag ' DR_Flag R A Latch the Data and the Strobe.
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Lec04 - ECE 212 Digital Circuits II Wednesday 6 February...

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