{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Cau 6 cache - CS4617 Computer Architecture Lecture 3 Memory...

Info icon This preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
CS4617 Computer Architecture Lecture 3: Memory Hierarchy 1 Dr J Vaughan September 15, 2014 1/25
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Important terms Cache fully associative write allocate Virtual memory dirty bit unified cache Memory stall cycles block offset misses per instruction Direct mapped write-back block Valid hit data cache locality Block address hit time address trace Table: Memory terms 2/25
Image of page 2
Important terms (ctd) Write-through Cache miss Set Instruction cache Page fault Random replacement Average memory access time Miss rate Index field Cache hit n-way set associative No-write allocate Page Least recently used Write buffer Miss penalty Tag field Write stall Table: Memory terms 3/25
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Term definitions 1 Cache The first level of memory met when the address leaves the processor. The word cache is often used to mean buffering commonly-used items for re-use Cache hit Success: finding a referenced item in cache Cache miss Failure: the required item is not in the cache Block The fixed number of bytes of main memory that is copied to the cache in one transfer operation. This transfer happens when a cache miss occurs Temporal locality A referenced item is likely to be referenced again in the near future Spatial locality Other data in the same block as a referenced item are likely to be needed soon 4/25
Image of page 4
Term definitions 2 Virtual memory The extension of memory to an address space that encompasses the physical residence on disk of some programs and data Page A fixed-size block of virtual memory address space, usually in the range 1K to 4K. A page is either in main memory or on disk Page fault An interrupt generated when the processor references a page that is neither in cache nor in main memory 5/25
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Term definitions 3 Memory stall cycles Number of cycles during which processor is stalled waiting for a memory access Miss penalty Cost per cache miss Address trace A record of instruction and data references with a count of the number of accesses and miss totals 6/25
Image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}