Exam 2 - EEL3701—Examll,Spr2007 Name: (€91 - UFID: -...

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Unformatted text preview: EEL3701—Examll,Spr2007 Name: (€91 - UFID: - COVER SHEET page Points Re-Grade Information: Remember to show ALL work for EVERY problem on the exam for partial credit! Pg. 1 0f7 EEL 3701 — Exam ll, Spr 2007 Name: Z2 2 UF ID: SRAMIROM Memory Related 1. Given a 64K x 16 SRAM, how many bits of RAM are available for programming? (3 pts.) 291w Wit 2. We would like to design a 64K x 24 block of ROM using 32K x 8 EPROMs. Draw the EPROMs required for this block of memory and label all signal connections to the EPROMS. Use bus style nomenclature on multiple signal paths (address & data buses) and show the required logic gates to enable & disable the 32K x 8 EPROMs as required to build the 64K x 24 block of ROM. (12 pts.) gc/L SP fl/SJ 0 g 4 way 32K fl/filfb D231; 1> DZBCD/é 05:? 1/ two equations: Y = AB + /A/B where Y.H, A.H, B.H and Z = A + B where Z.L, A.H, B.H (8 pts.) 4. Given the following/ROM and attached signals, show what must be programmed in memory for the following GND Address (Hex) Data (Hex) +5V A.H / 1/ B.H \‘Pg. 2 of7 EEL 3701 —- Exam ll, Spr 2007 Name: UF lD: Counter Design 5. Design a counter using the KG flip-flop below with the following specifications: If the input UP is true count O,l,2,3,4,0 else if UP is false count 4,3,2,1,0,4 KG condensed excitation table => Osi Xi H K 1&1 OOJH T G Q 490 ()1le C CLK 090 X0 S (CK I»; a) [)7 3) 50. Show the logic equations for the KG flip—flops assuming they will be placed in your CPLD. You do not need to simplify the equations and should write them as a simple sum of products. (6 pts.) or 90 3 K25 0 “i fig,“ 4 “fl, 1 Q 2 C (UP WQlQ03 4<UPQZ§§626>4 (fiQ’ZQlao)+(U101QLQ)QO) Ki :3 O 0“ 1 fl ~ ~ ‘ \ 6i 1 (uPQ-icSyQoH (UQgENlQO)+CWQZ&WO) +(ur mice) 1/ Kg 3 0 0v 5, w : (mama‘fumdzmmo) 3 mm EEL 3701 — Exam II, Spr 2007 Name: UF ID: Synchronous vs. Asynchronous Timing Diagram with an ASM 6. Given the following block diagram containing an ASM and extra circuitry, fill in the timing diagram that follows. Algorithmic 1N1 State Machine ASM Inputs: |N1.H, CLK D Flip—Flop: SET is asynchronous & high true ASM Outputs: SET.H, S1.H, SO.H, CLR.H CLR is asynchronous & high true ASM Flow Chart for the ASM Above: State 2 SLH, SO.H Pg. 4 of7 EEL 3701 — Exam H, Spr 2007 Name: K E i UF ID: 6a. Complete the Timing Diagram for State, 81, SO CLR, SET and OUT below based on the design on the previous page. (15 pts.) 4/ 'LO/li‘ Pg.50f7 UFlD: EEL 3701 — Exam ll, Spr 2007 Name: Pg.50f7 (10 pts.) (15 pts.) 6a. Complete the Timing Diagram for State, 81, SO CLR, SET and OUT below based on the design on the previous page. 6b. Complete the next state table required for the ASM on the previous page. EEL 3701 — Exam ll, Spr 2007 Name: UF ID: Computer Buses, Registers and ALU Design 7. Given the following Bus/ Register Hardware Diagram, answer the questions that follow. MUX Select Mag S3 = 0, IN7:0 => Common Bus S3 = l, OUT7:0 => Common Bus “LD_A ALU Function Map -OE_A 5; g; _s_() CLK 0 O 0 OUT = IN} 0 0 1 OUT = 1N2 O 1 0 OUT = 1N1 PLUS 1N2 _LD B 0 1 1 OUT = Complement (1N1) _OE—B l 0 0 OUT = 1N1 multiplied by 2 - 1 0 1 OUT = 1N1 divided by 2 CLK 1 1 0 OUT = 1N1 PLUS 1 1 1 1 OUT = IN 1 MINUS l -LD_C CLK 7a. We would like to load the number 55 Hex into Register B and then shift it right twice with the final result being placed in Register A. Show the minimal number of cycles required to do this. Show all true control signals required each cycle and the contents of the registers after each cycle. Assume that you will set up the control signals and then clock all registers at the same time. (8 pts.) 15 .5 l Pg.6of7 EEL 3701 — Exam ll, Spr 2007 Name: UF ID: 7b. Subtract 44 Hex from 33 Hex where both numbers are initially input as unsigned binary numbers. The final result should be in 2’complement format and stored in Register A. Show the minimal number of cycles to perform this and again show the register contents after the cycle is executed (clock is pulsed L,H,L). (7 pts.) C cle N0. IN7:O ReA RB ReC -LD A -OE A -LD B -OE B -LD C-OE C S3 82 S1 SO l xx 0 o o o H X)( 53 @ o o o o a @ o o o 3 xx XX 33 0 0 0 ’0 ® CD 4 xx xx 33 EC 0 O 63> ’0 (D 0 (CE 5 xx E? g3 BC @ o a (D a {it @' \‘9 Nor ling Him 01mm? Hammer: 73 won’t/Tums“: New £2: A WEE“ng Ema: O» maxim, Am: A firéazérEfl F62 1132; 70. Draw the circuitry required to create the MUX in the diagram on the previous page. (4 pts.) Pl IMO MO -—-—-—— 7d. If we assume th§§each of the functions in the ALU will be derived from a separate logic block how many and what ‘ size MUX is required at the output of the ALU to connect a particular function output to the output bus OUT720? (2 pts.) (g) gzl Muxzrs l l 7e. If you are given a 4 bit Full Adder block, show the circuitry required, using one or more of these 4 bit Full Adder blocks, to design the logic for the function in the ALU when 82 = 81 = 80 = 1. (4 pts.) Pg.7of7 ...
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Exam 2 - EEL3701—Examll,Spr2007 Name: (€91 - UFID: -...

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