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EE214 Winter 04/05
Handout #23
B. Murmann
Page 1 of 6
MIDTERM PROJECT
(Due: Wednesday, November 24, 2004, noon PT)
READ THIS
ENTIRE
HANDOUT THOROUGHLY!
Part 1: Design Specifications and Deliverables
Part 2: Spice Test Setup
Part 3: Project Submission Procedure
Your new job at ChipsForFree.com requires you to design of a high performance OTA
for use in a pipelined A/D converter. After an exhaustive study of the business
opportunity, your marketing department decides that the circuit shown in Figure 1 should
meet the following specifications:
Parameter
Specification
Static Gain Error
< 0.25%
Closed Loop 3dB Bandwidth
250MHz
Phase Margin
> 70
°
Power Dissipation
Minimize
C
s
+
V
sd

+
V
od

C
s
C
f
C
f
C
L
C
L
V
id
Figure 1
Given circuit parameters:
Last modified 11/1/2004 1:30 PM
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View Full DocumentEE214 Winter 04/05
Handout #23
B. Murmann
Page 2 of 6
Parameter
Value
Technology
EE214 0.35
µ
m CMOS
V
DD
3V
Input Common Mode Voltage
1.5V
Output Common Mode Voltage
1.5V
Differential Output Range*
4.2V
Operating Temperature
27
°
C
C
L
100fF
C
s
200fF
C
f
100fF
Compensation capacitors (if used)
>100fF
*Defined as the differential output swing at which the OTA’s Open Loop DC gain
V
od
/V
id
has dropped by 30% relative to its quiescent point value.
Additional design considerations and constraints
•
Current mirror ratios cannot be larger than 20, and must be integer.
•
Due to past failures at ChipsForFree.com, it is strictly forbidden to cancel
nondominant poles via feedforward zeros.
•
Your OTA must contain a suitable common mode feedback circuit. Since we want to
focus on the design of the differential signal path in this project, you can simply use
ideal common mode feedback, e.g. as used in homework 5.
•
Your final circuit may use no more than one ideal floating current source. In case you
decide to use cascodes in your design, you must generate all required bias voltages
using MOS transistors.
•
Note that before you could actually fabricate this design, several other aspects would
need to be factored into the design process. E.g. noise performance, and also slewing,
an effect that we’ll cover later in this class. To keep this project manage, we will
ignore these additional difficulties. In addition, you don’t need to consider process
and temperature variations. However, we still require that your circuit not be overly
sensitive to either (i.e., no “marble balanced on the tip of a cone” behavior). We will
be the final judges of whether such a condition exists. If you are unsure, please
consult the teaching staff early on.
Suggested design flow
As you will find out, this problem has many more degrees of freedom than all of the
homework assignments you have dealt with so far. Hence, we suggest that you tackle this
design in two steps. First, generate a reasonable design that meets the performance
requirements. E.g. pick reasonable L and g
m
/I
D
for all devices, calculate the required
transconductance(s) that are needed to meet the specs, and determine all currents and
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 Fall '04
 Murmann,B
 Integrated Circuit

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