hw1_sol - positive peak, which implies that V o2 is minimum...

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6) c) The derivation below makes no assumptions, other than that the above-calculated small signal voltage gain accurately predicts the voltage swings at V o1 and V o2 and that the quiescent points do not shift in presence of the signal. The first stage amplifies the input amplitude of 5mV to a swing of about 20mVpeak around the quiescent point of 1V at the gate of the NMOS device. V o2 swings around it’s quiescent point of V DD -1V with an amplitude of 4*20mV=80mV. The worst case for headroom considerations occurs when the NMOS gate voltage is at its
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Unformatted text preview: positive peak, which implies that V o2 is minimum and the minimum drain-to source voltage to keep the NMOS in saturation is at its maximum. We need to satisfy V o2,min > (V gs V t ) max , which means V DD-1.08V > 1.02V 0.5V VDD > 1.6V V o1 V o2 V DD 1V 1.02V 0.98V V DD-1V V DD-1.08V + V dsat-V DD-0.92V 20mVpeak swing 80mVpeak swing Note: Alternative/approximate solutions that make use of appropriate small signal assumptions will also yield full credit....
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This note was uploaded on 04/17/2008 for the course EE 214 taught by Professor Murmann,b during the Fall '04 term at Stanford.

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hw1_sol - positive peak, which implies that V o2 is minimum...

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