h11_hw3 - (see figure below). The goal of this problem is...

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EE214 Winter 04/05 Handout #11 B. Murmann Page 1 of 1 Last modified 10/11/2004 5:56 PM HOMEWORK #3 (Due: Monday, October 18, 2004, noon PT) 1. In this problem, you will use HSpice to generate a set of plots that are useful for all remaining design problems of this course, and in particular the midterm design project. a) Generate current density plots (slide 16, lecture 5) for NMOS devices of length 0.35…0.7 µ m in 0.05 µ m steps, all in one diagram. X-axis: 2/(g m /I D ), Y-axis: I D /W. b) Repeat part (a) for PMOS devices, using the same range of channel lengths. c) Generate transit frequency plots (slide 5, lecture 7) for NMOS devices of length 0.35…0.7 µ m in 0.05 µ m steps, all in one single diagram. Make sure to use the “C gg variable in your HSpice deck to account for extrinsic capacitances. X-axis: g m /I D , Y-axis: f T = (1/2 π ) g m /C gg . d) Repeat part (c) for PMOS devices, using the same range of channel lengths. 2. We will now use the design charts of problem 1 to design an NMOS common source stage
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Unformatted text preview: (see figure below). The goal of this problem is to help you become familiar with the g m /I D design methodology discussed in class. Given parameters: V DD =2V, R L =1k, R i =5k, A DC =2, maximum DC power dissipation P max =300 W. a) Calculate the required transconductance (neglect finite r o ). b) Find g m /I D , assuming that you are going to use the maximum available supply current. c) Determine the device width using the current density chart. d) Use the transit frequency chart to determine the device f T . Use the Miller approximation to calculate the bandwidth of the circuit. e) Verify the design using Spice. Deliverables: .OP bias point listing and plot of frequency response with annotated bandwidth. Quantify the % error in bandwidth between hand analysis and simulation. f) Repeat part (c)-(e) for L=0.5 m. What is the percent decrease in bandwidth? R L V o v i V I R i V DD 3. Text, Problem 7.33....
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