h36_lecture28_2

h36_lecture28_2 - Lecture 28 Technology Scaling Boris...

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EE 214 Lecture 28 (HO#36) B. Murmann 1 Lecture 28 Technology Scaling Boris Murmann Stanford University murmann@stanford.edu Copyright © 2004 by Boris Murmann EE 214 Lecture 28 (HO#36) B. Murmann 2 Overview Introduction – The trend of continuously shrinking feature sizes in integrated circuits has resulted in enormous performance gains in both digital and analog circuits. However, since device scaling necessitates the use of smaller supply voltages, it is often argued that noise limited circuits can no longer benefit from scaling. In this lecture, we will first review basic device performance trends in light of feature size reduction. Next we will look at a case study that aims to quantify the "figure of merit" of a noise limited transconductance stage versus technology scaling. In the end result, we will see that the impact of technology scaling and low supplies is not as severe as one may infer from superficial first order arguments.
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EE 214 Lecture 28 (HO#36) B. Murmann 3 The Age of "Moore's Law" In 1965, Gordon Moore predicted that there will be an exponential growth in the number of transistors per integrated circuit EE 214 Lecture 28 (HO#36) B. Murmann 4 … And He was Right [Moore, ISSCC 2003]
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EE 214 Lecture 28 (HO#36) B. Murmann 5 Smaller Minimum Feature Size EE 214 Lecture 28 (HO#36) B. Murmann 6 Faster
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EE 214 Lecture 28 (HO#36) B. Murmann 7 Cheaper Average Transistor Price EE 214 Lecture 28 (HO#36) B. Murmann 8 Misnomer
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This note was uploaded on 04/17/2008 for the course EE 214 taught by Professor Murmann,b during the Fall '04 term at Stanford.

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h36_lecture28_2 - Lecture 28 Technology Scaling Boris...

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