F2015-Lec-08_Verilog-2

# F2015-Lec-08_Verilog-2 - Verilog 2 EEM216A Fall 2015 Prof...

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Verilog 2 Prof. Dejan Marković [email protected] EEM216A Fall 2015

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D. Markovic / Slide 2 Four-Valued Logic Input = {0, 1, x, z} Output “Regular” gate: both inputs = {0, 1} “Dominant” input: {0, 1} combined with {x, z} Quadrant “X”: both inputs = {x, z} 8.2
D. Markovic / Slide 3 Four-Valued Logic: Rules z treated as an x on input Same rows and columns If you forget to connect an input, it will be seen as z At the start of simulation, everything is an x 8.3

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D. Markovic / Slide 4 “Regular” NAND Gate NAND 0 1 x z 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x Input A Input B 8.4
D. Markovic / Slide 5 “Dominant” Input NAND 0 1 x z 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x Input A Input B 8.5

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D. Markovic / Slide 6 Quadrant “X” NAND 0 1 x z 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x Input A Input B Unresolved cases: Out = x 8.6
D. Markovic / Slide 7 Behavioral Model 8.7

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D. Markovic / Slide 8 Preview: Dataflow vs. Behavioral Model (1) Dataflow All synthesizable Expression-based Only use wire and assign in each expression Mostly for design All expression are executed concurrently Behavioral Not all synthesizable Block-based Only use reg and procedural statement in each block Some for design, some for testbench 8.8
D. Markovic / Slide 9 Preview: Dataflow vs. Behavioral Model (2) Dataflow ( Lec . 6) Module, instance, port connection Net, register, number, assignment Vector, array, operator Behavioral (Today) Timing control basic (timescale, initial, always) Procedural (blocking/non-blocking) assignment Activation list, combinational, edge-trigger logic Conditional statement, level-trigger logic, for loop Useful syntax for testbench Remember: Testbench NEVER gets synthesized 8.9

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D. Markovic / Slide 10 Remember: wire vs. reg All outputs of an assign statement must be wire All outputs in an always / initial block must be reg Note: No restriction on the input (RHS) assign C = A + B ; (C must be wire ; A and B not restricted) initial #20 C = A + B ; (C must be reg ; A and B not restricted) 8.10
D. Markovic / Slide 11 Behavioral Model Template all behavioral models have following structures <Procedural block> <Activation list (optional)> <Sequential block begin > <Conditional statement> <Sequential block begin > <Sequential block end > <Procedural assignment w/ dataflow operator> <Syntax for testbench, e.g. \$finish (optional)> <Sequential block end > 8.11

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D. Markovic / Slide 12 Behavioral Models Timing control basic (timescale, initial, always) Procedural assignment (Blocking/Non-blocking) Activation list, combinational, edge-trigger logic Conditional statement, level-trigger logic , for loop Other useful syntax for testbench The mark on top of a page means “ synthesizable 8.12
D. Markovic / Slide 13 How Verilog Handles Timing • Remember we talk about “time unit (T.U.)” in Lec. 6 T.U. defined by timescale at beginning of a module: The amount of delay is relative to main scale .

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