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F15-216A-Hw2-sol

F15-216A-Hw2-sol - EEM216A Prof Dejan Marković Design of...

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Unformatted text preview: EEM216A Prof. Dejan Marković Design of VLSI Circuits and Systems Homework #2 Fall 2015 Due: Friday Oct 23 at 4pm Problem 1. Logic Design | Logical Effort Assume the mobility ratio, µn / µp = 2.5, CS/D = CG = C0. VDD A 24 C 12 D 8 12 B Out B A 6 12 C 12 D 12 a. What is the logic function of Out? (2p) Out = !!!!!!!!!!!!!!!!!! + ( + ) b. Which input has the lowest average delay to the output? (4p) A B C D Justification: B is closest to the output and it will be a “faster” input. You can also explicitly calculate the delays and see the result as outlined below (see part c for g and p calculation. dA_AVG = gA_AVG * hA + pA_AVG = 3.64 * (COUT/36) + 3.84 = 0.101*COUT + 3.84 dB_AVG = gB_AVG * hB + pB_AVG = 1.45 * (COUT/18) + 3.05 = 0.08*COUT + 3.05 dC_AVG = gC_AVG * hC + pC_AVG = 3 * (COUT/24) + 4.75 = 0.125*COUT + 4.75 dD_AVG = gD_AVG * hD + pD_AVG = 2.5 * (COUT/20) + 4.75 = 0.125*COUT + 4.75 c. What are the largest gavg (average worst-­‐case gup and gdown for an input) and largest pavg (average worst-­‐case pup and pdown for an input)? (4p) gAup = 36/5.6 gAdn = 36/42 gAavg = 3.64 gBup = 18/11.2 gBdn = 18/14 gBavg = 1.45 pBup = 38/11.2 pBdn = 38/14 pBavg = 3.05 gCup = 24/5.6 gCdn = 24/14 gCavg = 3 pCup = 38/5.6 pCdn = 38/14 pCavg = 4.75 gDup = 20/5.6 gDdn = 20/14 gDavg = 2.5 pAup = 38/5.6 pAdn = 38/42 pAavg = 3.84 pDup = 38/5.6 pDdn = 38/14 pDavg = 4.75 Max (gavg) = 3.64 (A) Max (pavg) = 4.75 (C, D) Problem 2. Flip-­‐Flops | Logical Effort Clk S Q D Clk 1 Fig. 2. Sequential Circuit. All transistors in the circuit have equivalent resistance R and gate capacitance C (ignore diffusion capacitances). Output is loaded with external capacitance CL = 16C. Calculate the propagation delay tClk-­‐Q (to output ) for high-­‐to-­‐low and low-­‐to-­‐high transitions. Ignore signal slopes in the delay calculation. 16C Q !"∗! !"!! Clk 1 tpHL = 0.69 (3R*2C + ( S D Clk tpHL )*4C + R*16C) = 18.24RC (stack PD + 2nd stage PU + inv PD) Clk 16C Q S 1 D S is already 1 Clk tpLH tpLH = 0.69 (( !"∗! !"!! )*4C + R*16C) = 22.86RC (2nd stage PD + inv PU) tpLH = 22.86RC tpHL = 18.24RC ...
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