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Unformatted text preview: i_passcode [7:0] Input secret sequence Outputs: Signal Name Bit Width Description o_locked  LOW:Unlocked; HIGH:Locked o_fake  HIGH when fake sequence detected a. Draw the state machine diagram for this lock module. Indicate all inputs and outputs as well as states. b. Write the Verilog module HW3_lock in a file called HW3_lock.v, and a testbench for this module called HW3_lock_tb in a file called HW3_lock_tb.v. Please submit HW3_lock.v and HW3_lock_tb.v. Make sure that the signal names are called exactly how they are specified here otherwise your design may fail grading. Problem 2. Flip-Flops Analysis Estimate the setup time of the flip-flop shown below. Assume that all evaluation paths (in each stage) are sized to have driving strength R, which is equal to that of reference inverter sized with Wp/Wn = 2. Assume that the input capacitance of the reference inverter is C and that Cpar/Cgate = 0.5. Estimate setup time in terms of RC. Reference: 2012 VLSI Circuits Symposium (paper 20.2) – available on the wiki....
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- Fall '15
- Input/output, Prof. Dejan Marković, VLSI Circuits and Systems, VLSI Circuits Symposium