F15-216A-Hw3 - i_passcode[7:0 Input secret sequence Outputs...

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EEM216A Design of VLSI Circuits and Systems Fall 2015 Prof. Dejan Markovi ć Homework #3 Due: Saturday Oct 31 at 4pm Problem 1. Verilog & State Machines Your task is to design a lock system which takes in a stream of 8-bit numbers as input and outputs the locked/unlocked state. The module is locked on reset (asynchronous, active low). The module will look for the sequence [244, 35, 244, 6, 157] and become unlocked only if this sequence appears at the input, while the input sequence is valid. Another input signal is used to lock the module. There is a fake sequence which is given out to suspicious people. When the sequence [88, 13, 244, 35, 90] is detected, an output indicating that a fake sequence was detected will go high. Once this occurs, the module should refuse to unlock until a reset signal is sent. Inputs: Signal Name Bit Width Description i_clk [0] Clock i_rst_n [0] Asynchronous reset, active low i_lock_en [0] When HIGH, change the state to LOCK i_passcode_valid [0] Only accept input sequence when this signal is HIGH
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Unformatted text preview: i_passcode [7:0] Input secret sequence Outputs: Signal Name Bit Width Description o_locked [0] LOW:Unlocked; HIGH:Locked o_fake [0] HIGH when fake sequence detected a. Draw the state machine diagram for this lock module. Indicate all inputs and outputs as well as states. b. Write the Verilog module HW3_lock in a file called HW3_lock.v, and a testbench for this module called HW3_lock_tb in a file called HW3_lock_tb.v. Please submit HW3_lock.v and HW3_lock_tb.v. Make sure that the signal names are called exactly how they are specified here otherwise your design may fail grading. Problem 2. Flip-Flops Analysis Estimate the setup time of the flip-flop shown below. Assume that all evaluation paths (in each stage) are sized to have driving strength R, which is equal to that of reference inverter sized with Wp/Wn = 2. Assume that the input capacitance of the reference inverter is C and that Cpar/Cgate = 0.5. Estimate setup time in terms of RC. Reference: 2012 VLSI Circuits Symposium (paper 20.2) – available on the wiki....
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