Damon Pryor lab 1

Damon Pryor lab 1 - Damon Pryor Lab 1 EECC351 Section 42...

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Damon Pryor Lab 1 EECC351 Section 42 Erik Golen (instructor) Micheal Micheal (TA)
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Test Methodology: To test the code for part one, the use of compiling was use to make sure the code was efficient and accurate. For part two, the signals were assigned in the lab by the user which allowed for waveforms to be created and used to make sure correct. In part three forces were used to cause the signals to be assigned different values that could then be verified using the wave form snap shot. APPENDIX 1a.) The code for Part one 2a.) The code for part two, the one with out the delay 2b.) The code for part two with the delay 3a.) The code for part three with assigned signal values 3b.) The code for part three with forced signal values 2c.) The wave form for part two, with out the delay 2d.) The wave form for part two with the delay 2e.) 3c.) The wave form for part three with forced values 3d.) The Force File
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1a) ----------------------- --File:: PartOne.vhd --Entity:LS181 --Architecture:n/a --Author: Damon Pryor --Created:12/13/2007 --Modified:12/13/2007 -- --VHDL '07 --Description: A four bit arithmetic Logic Unit --which provides 16 arithmetic operations an all 16 --logic operations through inputs A and B which are --Active Low, Input S witch are Select inputs, Input --M which is Control Input. Input C which is Carry --Input. The Results are Given through output F which --are Active low, output G which is Generate Output
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Damon Pryor lab 1 - Damon Pryor Lab 1 EECC351 Section 42...

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