lab6 - Damon Pryor and J. Daniel Behun Lab 6 EECC351...

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Damon Pryor and J. Daniel Behun Lab 6 EECC351 Section 42 Class Section 02 Erik Golen (Lab Instructor) Micheal Micheal (TA) Dr. K (Class Instructor)
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Test Methodology This lab was created to teach many concepts, basically the ones that were not reached by the end of the quarter. It required that the participants create two general multipliers, one that’s signed and another that is unsigned. The un-signed multiplier was to be created structurally. This was done in this lab by using a two input and-gate, a half adder, and a full adder. To make it general generic statements were used to create a variable to judge the varying length by. To make the array the right side the use of generate statements were used. To test the functionality this lab design used two test benches. The first test bench generated a file of all the possible input values that the program was too run through. The second test bench took that file and executed for every possible outcome. After this the lab called for the signed multiplier. This was to be a general multiplier also this difference this time was that booth’s algorithm was to be used to do the multiplication, as well as it was to be done in a behavioral manner. Booth’s algorithm called for the two registers to first be loaded then the lower two bits of the B register were to be tested. If the two lower bits are 01 then register C was to be added to register A. If the two lower bits are 10 then the 2’s complement of C was to be added to register A. If the two lower bit are anything else it was to skip the addition all together. The unsigned multiplier was then to shift the values of A and B. It then repeated this until the desire answer was received.
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Appendix 1a.) Unsigned Mulitplier code 2a.) Full Adder code 3a.) Full Adder with Delay code 4a.) Half Adder code 5a.) Half Adder code 6a.) And Gate code 7a.) Testbench to create a file code 8a.) Testbench to simulate the Muliplier code 1b.) Wave snapshot 1 1c.) Wave snapshot 2 1d.) Wave snapshot 3 1e.) Block Diagram 1f.) Error Message 1g.) Synthesis Description 1 1h.) Synthesis Description 2
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1a ------------------------------------------------- -- File: CBM.vhd -- Entity: Ent_Mult -- Architecture: Arch_Mult -- Author: Damon Pryor -- Created: 2/14/08 -- Modified: 2//08 -- -- VHDL'93 -- Description: A complicated combinational binary multiplier -- ------------------------------------------------- library ieee; use ieee.std_logic_1164.all; Entity Ent_Mult is generic (n:integer:=4); port( x,y : in std_logic_vector(n-1 downto 0); p : out std_logic_vector (2*n-1 downto 0)); end Entity Ent_Mult; Architecture Arch_Mult of Ent_Mult is component AND2 is port(A,B : in std_logic; D : out std_logic); end component; component FullAdder is port(A : in std_logic; B : in std_logic; C : in std_logic; sum: out std_logic; Carry: out std_logic); end component FullAdder; --Full adder takes in 4 signals and the outputs 2 component HalfAdder is --unlike the FullAdder, the half adder takes in 2 signals port( A, B : in std_logic;
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This note was uploaded on 04/17/2008 for the course CE 0306-351-0 taught by Professor Dr.k during the Winter '07 term at RIT.

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lab6 - Damon Pryor and J. Daniel Behun Lab 6 EECC351...

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