Test Methodology

Test Methodology - flops as well and numerous And Gates and...

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Test Methodology This lab was meant to teach how to use a serial adder with a Finite State Machine to eliminate the wait statements used in the previous lab when generating signals. This was to be done by creating a behavioral and structural state machine to generate the proper signals. While the behavioral state machine layout was outlined in the lab the structural state machine had to be created by using K-maps. The K-maps were used to discover the components needed as well as the next state logic and output signals. Once discovered a schematic diagram of the state machine was derived. This yielded 7 flop-
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Unformatted text preview: flops as well and numerous And Gates and Or Gates. It also required a inverter to invert the start signal in certain places. All of this needed to be tested by a test bench, which took advantage of a generator to make sure of the functionality of each component and element. From there this was to be connected to the serial adder created in lab4, with the purpose of eliminating the wait statements which are not legitimate in synthesis. All of this would have worked quite nicely if functional, however in the waveforms presented in this lab report its clear that it did not work....
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