lab5 - Damon Pryor Lab 5 EECC351 Section 42 Class Section...

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Damon Pryor Lab 5 EECC351 Section 42 Class Section 02 Erik Golen (instructor) Micheal Micheal (TA)
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Test Methodology This lab was meant to teach how to use a serial adder with a Finite State Machine to eliminate the wait statements used in the previous lab when generating signals. This was to be done by creating a behavioral and structural state machine to generate the proper signals. While the behavioral state machine layout was outlined in the lab the structural state machine had to be created by using K-maps. The K-maps were used to discover the components needed as well as the next state logic and output signals. Once discovered a schematic diagram of the state machine was derived. This yielded 7 flop- flops as well and numerous And Gates and Or Gates. It also required a inverter to invert the start signal in certain places. All of this needed to be tested by a test bench, which took advantage of a generator to make sure of the functionality of each component and element. From there this was to be connected to the serial adder created in lab4, with the purpose of eliminating the wait statements which are not legitimate in synthesis. All of this would have worked quite nicely if functional, however in the waveforms presented in this lab report it’s clear that it did not work.
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---------------------- --File: hw5.vhd -- --Entity: ud --Architecture: udcount --Author: Damon Pryor --Created: 02/13/2008 --Modified: -- --VHDL 93 --Description: --------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity udc is port( pload:in std_logic_vector(0 to 7) := "00000000"; clk:in std_logic; control:in std_logic_vector(0 to 1); reset:in std_logic; output:inout std_logic_vector(0 to 7) ); end entity udc; architecture udcounter of udc is begin process (clk, reset) variable oldouts:std_logic_vector(0 to 7); begin oldouts := output; if reset = '1' then output <= "00000000"; elsif rising_edge(clk) then case control is when "11" => oldouts := pload; when "10" => oldouts := oldouts + '1'; when "01" => oldouts := oldouts - '1'; when others => null; end case; output <= oldouts; end if; end process; end architecture udcounter;
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Appendix 1a.) And Gate code 2a.) Or Gate code 3a.) Flip Flop code 4a.) Inverter code 5a.) Behave State and Structural State code 6a.) TestBench code 5b.) Testbench1 Wave Total 5c.)Testbench2 Wave Zoomed In
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lab5 - Damon Pryor Lab 5 EECC351 Section 42 Class Section...

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