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Damon Pryor lab 2

Damon Pryor lab 2 - Damon Pryor Lab 2 EECC351 Section 42...

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Damon Pryor Lab 2 EECC351 Section 42 Erik Golen (instructor) Micheal Micheal (TA

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Test Methodology: While the source code complied it could not be tested do to the inability to create working test benches. Questions: For this lab there was no questions asked. APPENDIX 1a.)The code for Part one a 2a.)The code for part one b 3a.)The code for part one c 1b.)The wave for part one a 2b.)The wave for part one b 3b.)The wave for part one c 1c.) The force file for part a 2c.) The force file for part one b 3c.) The force file for part one c
1.) ------------------------------------------------- -- File: parta.vhd -- Entity: Multi -- Architecture: CSA -- Author: Damon Pryor -- Created: 1/9/08 -- Modified: 1/09/08 -- -- VHDL'93 -- Description: This is and example of combinational -- signal assignment, thus uses else statements ------------------------------------------------- library ieee; use ieee.std_logic_1164.all; Entity LS153_3 is port ( G1 : in std_logic; G2 : in std_logic; A : in std_logic; B : in std_logic; C1 : in std_logic_vector(3 downto 0); C2 : in std_logic_vector(3 downto 0); Y1 : out std_logic; Y2 : out std_logic); end Entity LS153_3; Architecture CSA of LS153_3 is begin Y1<= (C1(0) AND (not G1)) when A = '0' and B = '0' else (C1(1) AND (not G1)) when A = '0' and B = '1' else (C1(2) AND (not G1)) when A = '1' and B = '0' else (C1(3) AND (not G1)) when A = '1' and B = '1'; Y2<= (C2(0) AND (not G2)) when A = '0' and B = '0' else (C2(1) AND (not G2)) when A = '0' and B = '1' else (C2(2) AND (not G2)) when A = '1' and B = '0' else (C2(3) AND (not G2)) when A = '1' and B = '1'; end Architecture CSA;

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------------------------------------------------- -- File: Testbench.vhd -- Entity: Testbench -- Architecture: TB -- Author: Damon Pryor -- Created: 1/13/08 -- Modified: 1/14/08 -- -- VHDL'93 -- Description: Tests partc of the package which -- contains the two multiplexers ------------------------------------------------- library ieee; use ieee.std_logic_1164.all; Entity Testbench is end entity Testbench; Architecture TB of Testbench is Component LS153_3 port ( G1 : in std_logic; G2 : in std_logic; A : in std_logic; B : in std_logic; C1 : in std_logic_vector(3 downto 0); C2 : in std_logic_vector(3 downto 0); Y1 : out std_logic; Y2 : out std_logic); end Component LS153_3; signal T1,T2, T3, T4, T_Out1, T_Out2 : std_logic; signal T_CO1, T_CO2 : std_logic_vector (3 downto 0); for DUT1 : LS153_3 use entity work.LS153_3(CSA); begin DUT1 : LS153_3 port map (G1=>T1, G2=>T2, A=>T3, B=> T4,C1=> T_CO1, C2 => T_CO2, Y1 => T_OUT1, Y2 => T_OUT2 ); end Architecture;
2a.)

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