Lab4 - Damon Pryor Lab 4 EECC351 Section 42 Class Section...

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Unformatted text preview: Damon Pryor Lab 4 EECC351 Section 42 Class Section 02 Erik Golen (instructor) Micheal Micheal (TA) Test Methodology For this lab, the design of 5 components was needed. One was of a 1 bit full_adder which was to be constructed using 8ns delays. Another was a D-FlipFlop with was to contain an enable, an Asynchronous reset as well and introduce 2 second delays. After this a 2-input and gate was needed which introduced. Lastly the lab specifications called for a 4 bit parallel shift register using internal signals. These components were to make up the structural design of the serial adder. 1.) Synchronous Logic compared to Combinational logic is that Synchronous occurs all at the same time . 2.) Speed and It saves time. In_A In_B Sum carry X ”0” X”4” X”4” ‘0’ X ”C” X”E” 1010 ‘1’ X ”8” X “A” 0010 ‘1’ X “F” X “F” 1110 ‘1’ X “F” X “1” 0000 ‘1’ X “A” X ‘5’ X “2” ‘0’ X “8” X “7” 1111 ‘0’ Appendix 1a.) And Gate code 2a.) Full Adder code 3a.) Flip Flop code 4a.) Shift Register code 5a.) Serial Adder code 6a.) TestBench code 5b.) Serial Adder Schematic 6b.) Test Bench Schematic 5c.) Shift Register Wave Total 5d.)Shift Register Wave Zoomed In 1a--------------------------------------------------- File: And2 -- Entity: And2-- Architecture:AndG-- Author: Damon Pryor-- Created: 1/22/08-- Modified: 1//08-- -- VHDL'93-- Description:-- This is an and gate which has an inverter on the A signal------------------------------------------------- library ieee; use ieee.std_logic_1164.all; Entity And2 is port( A,B : in std_logic; C : out std_logic); end Entity And2; Architecture AndG of And2 is begin process(A,B) begin C <= Not A and B after 4 ns; end process; End Architecture; 2a--------------------------------------------------- File: Full Adder -- Entity: FullAdder-- Architecture: -- Author: Damon Pryor-- Created: 1/22/08-- Modified: 1/24/08-- -- VHDL'93-- Description:-- takes the sum of the a or b or c, and also outputs the rest of signals as a carry------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity FullAdder is port(A : in std_logic; B : in std_logic; C : in std_logic; sum: out std_logic; Carry: out std_logic); end entity FullAdder; Architecture FA of FullAdder is signal s1, s2 , s3 : std_logic; begin process (A,B,C) begin sum <= A xor B xor C after 8 ns; Carry <=(A and B) or (A and C) or (B and C) after 8 ns; end process; end architecture; 3a...
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This note was uploaded on 04/17/2008 for the course CE 0306-351-0 taught by Professor Dr.k during the Winter '07 term at RIT.

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Lab4 - Damon Pryor Lab 4 EECC351 Section 42 Class Section...

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