Altera_Quartus_tutorial2 - UNIVERSITY OF CALIFORNIA, DAVIS...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I FALL 2008 Advanced Altera Quartus II Tutorial OVERVIEW This tutorial illustrates several advanced topics that were not covered in Lab 1. These topics include creating symbols for use in a hierarchical design, using Altera parameterized modules, such as a ROM, and initializing ROM contents. In this tutorial, you will design a circuit that computes the Fibonacci sequence using an adder and registers. (The Fibonacci sequence is 0, 1, 1, 2, 3, 5, 8, . ..) The data path will be 8-bits wide so that the circuit can be easily tested using the Altera Education Board. (If you thought a sequence of numbers could never be very interesting or have any applications, read up on the Fibonacci sequence—google it or check out ) USING PARAMETERIZED MODULES Select File>New Project Wizard… in order to create a new project. On page 1 of the dialog boxes, select a new project directory, and name the project and the top level entity “ fib ”. On page 3, select ‘ Flex10K ’ as the device family, select ‘ Specific device selected in ‘Available devices’ list ’ for the target device, and select ‘ EPF10K20RC240-3 ’ from the list of available devices. You can click ‘ Next ’ to see the remaining pages and configuration summary. Finally, select ‘ Finish ’. Open a new schematic and save it as ‘ fib.bdf ’. You will be designing the schematic shown in Figure 1. First, select the component lpm_add_sub from the megafunctions/arithmetic library. The MegaWizard Plug-In Manager should come up to allow you to configure the parameters and ports. If given the option, select the type of output file that will be created to describe your lpm modules as Verilog. Check the box that says “ Don’t ask me for an output file name or the output file format again. ” On page 1, select FLEX10K as the currently selected device family (or make sure the “ Match project/default ” box is checked). Also select the data buses to be 8 bits wide and the operating mode to be “ Addition Only ”. On page 2, allow both ‘dataa’ and ‘datab’ to vary and select ‘ Unsigned’ for the type of addition/subtraction. On page 3, select Create a carry input ’ and ‘ Create a carry output ’. On page 4, accept the default configuration that the module will not be pipelined. Finally, select “Finish” on the last page to complete the configuration. Place the lpm_add_sub component near the middle of your schematic page as shown in Figure 1. If you need to change any parameters or port declarations after you have closed the wizard, double-click on the lpm_add_sub component on your schematic. This will re-open the wizard so that you can make corrections. The adder will be used to add the last two numbers in the sequence to produce the next number.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/01/2009 for the course EEC 180A taught by Professor Redinbo during the Fall '08 term at UC Davis.

Page1 / 8

Altera_Quartus_tutorial2 - UNIVERSITY OF CALIFORNIA, DAVIS...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online