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Unformatted text preview: ALU Learning Goal: testbench, gate level simulation Requirements: Quartus II Web Edition and ModelSim. 1 Introduction In this lab you are going to implement a complete ALU and learn how to make testbenches and gate level simulations. 2 ALU description An ALU ( Arithmetic Logic Unit ) is a combinatorial circuit performing arithmetic and logical operations. Its the central execution unit of a CPU, and its complexity can vary. A simple ALU has two inputs for the operands, one input for a control signal that selects the opera tion, and one output for the result. The following figure is the common representation of an ALU. For this lab you have to implement a 32bit ALU with 4 internal units. Unit names, available opera tions and corresponding encoding are listed in the next table. Version 1.6 of 30th September 2008, EPFL 2008 1 of 8 ALU Operation Type Opcode A + B Add/Sub 000 A B 001 A B (signed) Comparison 011001 A < B (signed) 011010 A 6 = B 011011 A = B 011100 A B (unsigned) 011101 A < B (unsigned) 011110 A nor B Logical 10 00 A and B 10 01 A or B 10 10 A xor B 10 11 A rol B Shift/Rotate (Optional) 11 000 A ror B 11 001 A sll B 11 010 A srl B 11 011 A sra B 11 111 = dont care The 6bit op control signal can select one these operations. Notice that the 2 most significant bits, op 5 .. 4 , select the operation type (e.g., Add/Sub, Compari son, Logical). The op 3 bit is used to activate the subtraction mode of the Add/Sub unit. Notice that the subtrac tion mode is always activated for the comparisons and ignored for the logic and shift unit. We will see later that the comparator unit needs the result of the substraction to perform a comparison. The remaining bits, op 2 .. , select a specific operation of the comparator, logic or shift unit. The following figure shows the internal structure of the ALU. In the following subsections, each internal unit is descibed in more details. You can skip that for the moment, and start with the exercices of section 3. 2 of 8 Version 1.6 of 30th September 2008, EPFL 2008 ALU 2.1 Add/Sub The Add/Sub unit performs 32bit additions and subtractions. The sub input signal the activates subtraction mode . The carry output signal is the carry out of the internal adder. The zero output signal indicates whether the result is equal to 0. You can see the internal architecture of the Add/Sub unit in the following schema. When the subtraction mode is activated, we have to replace the B operand by its twos complement. The conditional B inversion can be done with 32 XOR gates: when sub is high B is inverted; otherwise it keeps its original value. The conditional increment in case of a subtraction mode can be done by connecting the sub signal directly to the carry in of the adder, then we will have A + B + 1 which is equivalent to A B ....
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This note was uploaded on 02/01/2009 for the course EEC 180A taught by Professor Redinbo during the Fall '08 term at UC Davis.
 Fall '08
 REDINBO

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