notRnotS_NANDlatch

notRnotS_NANDlatch - notR notS NAND Latch A C D B 00 Inputs...

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notR notS NAND Latch A B C D Inputs AB Inputs AB 00 01 10 11 00 01 10 11 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 Present State CD Next State C + D +
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A B C D notRESET Input B=0 D=1 notSET Input A=0 C=1 SET Output RESET Output + DC + B = + CD + A = Inputs AB Inputs AB 00 01 10 11 00 01 10 11 00 00 00 00 11 11 11 11 01 01 01 01 11 11 01 01 10 10 10 10 11 10 11 10 11 11 11 11 11 10 01 00 Present State CD Next State C + D + Stay Out Require A+B=1
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This note was uploaded on 02/01/2009 for the course EEC 180A taught by Professor Redinbo during the Fall '08 term at UC Davis.

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notRnotS_NANDlatch - notR notS NAND Latch A C D B 00 Inputs...

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