Huang2004

Huang2004 - 210 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL....

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Unformatted text preview: 210 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 3, NO. 1, MARCH 2004 Toward Long-Term Retention-Time Single-Electron-Memory Devices Based on Nitrided Nanocrystalline Silicon Dots Shaoyun Huang, Kenta Arai, Kouichi Usami, and Shunri Oda , Member, IEEE Abstract A memory capacitor with a structure of SiSiO P /nc-Si dots/silicon nitride films/SiO P was prepared by means of nc-Si dot deposition followed by N P plasma nitrida- tion processes. The memory device offers dual memory nodes: nc-Si dots and traps in siliconnitride films. An enlarged memory window in CV characteristics was observed in memory operations, due to the extra traps in siliconnitrides. The charge-loss rate was found to be much smaller than that of single memory nodes using nc-Si dots only. The provided larger memory window (about twice the width) and longer retention time in the memory operations (three orders of magnitude) are discussed in terms of trap-assisted charging/discharging mechanisms. Index Terms Charge carrier processes, memories, MOS devices, nanotechnology, quantum dots. I. INTRODUCTION B OTH nanocrystalline silicon (nc-Si) dot [1] and oxide- silicon nitride-tunnel oxide (ONO) [2] based nonvolatile memory devices have received much attention recently as a re- sult of continued scaling of MOSFETs where nc-Si dots and traps of nitrides, respectively, act as discrete memory nodes. In these kinds of devices, stored electrons can be operated one by one, and few or even one single electron can guarantee a reliable memory state, referred to as the single electron memory (SEM) [3], [4]. However, in spite of the successful demonstrations of memory operations and obvious advantages, the charge reten- tion time of both memories is too short for practical nonvolatile memory applications [1][4]. To improve charge retention time with little cost of the write/erase time, it is possible to take advantage of trap-assisted charging/discharging operations [5] that need thermal excitation processes. Nevertheless, the ONO based memories suffer from a higher operation voltage, due to the larger dielectric constants for Si N than for SiO , and unknown trap distributions, which al- ways give rise to variations in the threshold voltage between devices. nc-Si dot based memories can offer a well-controlled memory node positioning, relying on modern nanotechnologies [6], [7]. Therefore, a memory architecture using nc-Si dots cov- Manuscript received June 5, 2003; revised November 19, 2003. This work was supported in part by a grant-in-aid for Scientific Research from the Ministry of Education and in part by the Core Research for Evolutional Science and Tech- nology (CREST) program of the Japan Science and Technology Corporation (JST)....
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Huang2004 - 210 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL....

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