lecture_11_12 - Lecture 11-12 MOS-Capacitor Topics MOS...

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MOS-Capacitor Topics MOS Capacitor in equilibrium MOS Capacitor under bias -Capacitance -Accumulation -Depletion -Inversion Reading Assignment Howe Chap 3, Lecture 11-12
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MOS devices and by extension MOS capacitors are at the heart of the electronics revolution MOS capacitors and transistors are responsible for Charge Coupled Devices (CCD’s), Digital and Analog devices, CPU’s, memories, etc
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Metal: does not tolerate volume charge-> charges only exist on the surface Oxide: (perfect) insulator->no volume charge Semiconductor can have volume charge Thermal equilibrium cannot be established through the oxide because the carriers cannot equilibrate. A wire connection between the metal and the semiconductor Thermal equilibrium can be established by diffusion of carriers from the metal to the p-type semiconductor
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The carrier density is shown above. Far away from the interface the carriers are in a quasi neutral region. Near the oxide interface there is a reduction in the amount of holes and a corresponding increase in the number of minority carriers. The reduction in holes are a result of electron transfer from the surface metal to the metal contact to the p-region and the subsequent transfer of charge from the interface. Remember the law of mass action np=n i 2
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We can model the device quantitatively by using the depletion approximation. The charge configuration which is to be calculated is shown to the left. The charge on the metal surface is shown as a 2D charge density. As with the PN junction there must be a overall charge neutrality 0 ) ( ) ( 0 0 ) ( 0 ) ( ) ( 0 0 0 0 0 0 = < - = < < = < < - - = - x x x qN x x x x x t t Q x t x d a d ox ox G ox ρ ρ ρ δ ρ
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Integrate Gauss’s equation = - 2 2 ) ( 1 ) ( ) ( 0 1 0 2 0 x x dx x x E x E ρ ε At the interface between the oxide and the semiconductor there is a discontinuity due to a change in the permitivity 3 2245 = = ox s s ox s s ox ox E E E E ε ε ε ε
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0 ) ( ) 0 ( ) ( 0 ) ( ) ( 0 0 ) ( 0 0 0 0 0 0 0 0 0 = - < = = = < < - - - = < < = < + x E t x x qN x E x E x t x x qN x E x x x E x x ox ox d a o ox s x d s a d d ε ε ε ε Integrating right to left
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The boundary conditions on the potential need to be defined since we know the doping of p region Na we know p 0 and n o in the quasi neutral region. Since we are using poly Si as the metal gate we also know the doping in the poly Si which is N + . Therefore we can calculate both φ n + as well as φ p i p i n n p q kT n n q kT 0 0 ln ln - = = + φ φ i a p a n g d n N q kT N p QNR p N n gate n ln : : 0 0 - = = = = + + + φ φ φ Built in potential i a n p g B n N q kT ln + = - = + φ φ φ φ
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+ = - < - + + = < < - - + = < < = < n ox ox a s d a p ox d s a p d p d x t x x qN x qN x x t x x qN x x x x x x φ φ ε ε φ φ ε φ φ φ φ ) ( ) ( 2 ) ( 0 ) ( 2 ) ( 0 ) ( 0 2 0 0 2 0 0 0 0
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In order to find x no we need to solve the following KVL like equation ox ox d a s do a oxo B B t x qN x qN V
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