Assignment 3

# Assignment 3 - EE M16 Logic Design of Digital Systems Fall...

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EE M16: Logic Design of Digital Systems Fall 2015 Assignment #3 — due Monday, October 26, 2015 Instructor: Prof. Danijela Cabric Scribe: Ghaith Hattab Exercise A1 ( Multiplexer ). (a) How many 4-input multiplexers are needed to implement a 256-input multiplexer? (b) How many levels will there be? Exercise A2 ( Design ). Analyze the network shown in the figure below and design a gate network using AND, OR, XOR, and NOR gates that implements the same function. (Hint: z = 1 if the inputs to the decoder and the multiplexer are identical. Implement an equality comparator using XOR gates and one NOR). Ͳ തܽ ͳ ܽ ݓ 08; 3 4 5 6 ܾ ܿ 3 4 ݁ ݀ 'HFRGHU 3 4 5 6 (Q 7 9 : < 5 4 3 4 08; 3 4 5 6 7 9 : < ݖ ݃ ݄ 3 4 ݂ 5 Exercise A3 ( Logisim ). Implement a 5 -→ 32 decoder using a 2 -→ 4 and a 3 -→ 8 decoder as building blocks. Please capture the schematics in Logisim and attach them to the homework (Don’t submit electronic

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Unformatted text preview: ﬁles). Exercise 10.18 ( Bit Counting circuit, design ). Using full adders, design a circuit that accepts a seven-bit input and outputs the number of inputs that are 1 as a three-bit binary number. 1 EE M16 Assignment 3 — Monday, October 26, 2015 Fall 2015 Exercise 10.44 ( Five-times circuit ). Using adders, combinational building blocks, and gates, design a circuit that accepts a four-bit 2’s complement binary input a [3 : 0] and output a seven-bits 2’s complement output b [6 : 0] that is ﬁve times the value input. You cannot use a multiplier building block. Use the minimum number of adder bits possible. 2...
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• Fall '11
• cabriv
• Input/output, EE M16

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