Assignment2 - EE M16 Logic Design of Digital Systems Fall...

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EE M16: Logic Design of Digital Systems Fall 2015 Assignment #2 — due Monday, October 19, 2015 Instructor: Prof. Danijela Cabric Scribe: Mihir Laghate Exercise 6.8 ( Combinational design ). Design a minimal CMOS circuit that implements the function f = m (3 , 4 , 5 , 7 , 9 , 13 , 14 , 15). Exercise 6.11 ( Non-unique cover ). Design a four-input circuit that implements the function f = m (0 , 1 , 2 , 9 , 10 , 11). Exercise 6.46 ( Adder Karnagh maps, I ). A half adder is a circuit which takes in one-bit binary numbers a and b and outputs a sum s and a carry out co . The concatenation of co and s , i.e., co, s , is the two-bit value that results from adding a and b (e.g., if a = 1 and b = 1, s = 0 and co = 1.) Half adders are described in more detail in Chapter 10. (a) Write out truth tables for the s and co outputs of a half adder. (b) Draw Karnaugh maps for the s and co outputs of the half adder. (c) Circle the prime implicants and write out the logic equations for the s and co outputs of the half adder. Exercise 6.47 ( Adder Karnaugh maps, II ). A full adder is a circuit which takes in one-bit binary numbers a , b , and ci (carry in), and outputs s and co . The concatenation of co
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Unformatted text preview: s , i.e., { co, s } , is the two-bit value that results from adding a , b , and ci (e.g., if a = 1, b = 0, and ci = 1 then s = 0 and co = 1.) Full adders are described in more detail in Chapter 10. (a) Write out the truth tables for the s and co outputs for the full adder. (b) Draw Karnaugh maps for the s and co outputs for the full adder. (c) Circle the prime implicants and write out the logic equations for the s and co outputs of the full adder. (d) How would the use of an XOR gate help in the half adder? How would it help in the full adder? Exercise ( Logisim ). Implement the logic function f ( x, y, z ) = ( xy ) + ( x z ) . Test the output of function f ( x, y, z ) using different input combinations in Logisim and fill the following truth table. 1 EE M16 Assignment 2 — Monday, October 19, 2015 Fall 2015 x y z f ( x , y , z ) 1 1 1 1 1 1 1 1 1 1 1 1 Verify the Logisim outputs using the results calculated from Boolean algebra. 2...
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  • Fall '11
  • cabriv
  • Boolean Algebra, Half adder, Logical conjunction

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