Assignment 4

# Assignment 4 - EE M16 Logic Design of Digital Systems Fall...

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EE M16: Logic Design of Digital Systems Fall 2015 Assignment #4 — due Monday, November 9, 2015 Instructor: Prof. Danijela Cabric Scribe: Ghaith Hattab Important Note : The HW should be submitted in CORES lab 54-130B in Eng. IV between 10am and 12pm on Monday (there will be no lecture on that day). Exercise 14.9 ( Modified traffic-light controller, III-I ). Modify the traffic-light controller FSM of Table 14.4 so that the FSM stays in state GEW as long as carew is true. Show a state table and state diagram for your new FSM. Exercise 14.10 ( Modified traffic-light controller, III-II ). Choose a state assignment for the modified traffic- light controller of Exercise 14.9 and derive the logic to compute the next-state and output values. Show Karnaugh maps for the next-state variables and output variables and a gate-level schematic for the FSM. Exercise A1
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Unformatted text preview: ( Logisim ). Implement Exercise 14.10 using Logisim. Please capture the schematics in Logisim and attach them to the homework (Don’t submit electronic ﬁles). Exercise A2 ( State Description ). A sequential system has one input with values a , b , and c , and one output with values p and q . The output is q whenever the input sequence has an even number of a ’s and an odd number of b ’s. Obtain a state description of the system. Exercise A3 ( Sequence Pairs ). For the system described by the state diagram shown in the ﬁgure below, we want to describe the time behavior from t 1 = 5 to t 2 = 16 assuming that the initial state for t is s 3 . How many sequence pairs would be needed? Give three diﬀerent sequence pairs. Ͳ Ͳ Ͳ ͳ ܵ ଴ Ȁܽ ܵ ଵ Ȁܽ ͳ ܵ ଷ Ȁܿ Ͳ ͳ ͳ ܵ ଶ Ȁܾ 1...
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• Fall '11
• cabriv
• Modiﬁed traﬃc-light controller

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