381 HW 7 - CprE381 HW 7 P1(a Write MIPS assembly code...

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CprE381 HW 7 P1. (a) Write MIPS assembly code sequence (not a procedure call) to conditionally add two registers r1 and r3 and store result back in r1 if bit 0 of register r2 is a 1. Else r1 remains unchanged. andi $t0, $r2, 1; addi $t1, $0, 1; beq $t0, $t1, ADD; add $r1, $r1, $0; CONTINUE: .... .... ADD: add $r1, $r1, $r3; j CONTINUE (b) Write MIPS assembly code sequence to extract bit 0 of register r1 in register r4 at bit position 31. All other bits of register r4 should be set to zero. andi $t0, $r1, 1; addi $t1, $0, 1; beq $t0, $t1, ADDONE; lui $r4, 0x0000; ori $r4, $r4, 0x0000; CONTINUE: ..... ADDONE: lui $r4, 0x8000; ori $r4, $r4, 0x0000; j CONTINUE; (c) Write MIPS assembly code sequence to shift contents of register r2 right. The most significant bit of register r2 should be set to be the same as bit 31 of register r4. You can assume that all other bits of register r4 are set to 0. lui $t0, 0x8000; ori $t0, $t0, 0x0000; andi $t0, $r4, t0; srl $r2, $r2, 1; or $r2, $r2, $t0; P2. (20 points) Different execution units and blocks of digital logic have different latencies (time needed to do their work). Consider Figure 4.2 that depicts seven kind of major blocks.
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  • Spring '14
  • Most significant bit, Least significant bit, MIPS assembly code, assembly code sequence

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