Lecture_16_17_first_posting

Lecture_16_17_first_posting - Lecture 16-17 MOSFET Bias...

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MOSFET Bias Circuits and Large-Signal/ Small-Signal Single-Stage Operations What you will learn: Simple MOSFET-resistor DC circuits Source degenerate resistance biasing Current mirror biasing Common-source amplifier characteristics Common-gate and common-drain (source follower) Textbook reading: Sedra Chap 4, 6.3, 6.6, 6.8 Lecture 16-17
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Familiar with MOSFET DC I-V: RTL The MOSFET is diode connected: V GS =V DS , and in saturation. Use KVL to find I D : I D V th V D Load line plot 3V -1/R ( 29 2 ' 2 3 th D n D D D V V k L W I V V RI - = = + large signal or quasi-static V ref
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Example: Current Mirror Preview I 1 I 2 I 1 is entirely set by the right-hand side as the load line plot previously. • If Q 2 is in saturation also, since V GS1 =V GS2 • If R 2 is too large (or V DS2 = 3 - I 2 R 2 is smaller than V Dsat ), Q 2 will be in the linear region, and current mirroring disappears (note that I D is constant only in saturation). ( 29 ( 29 1 1 2 2 / / I L W L W I Q Q = View as a current source by tuning R Fig. E4.12
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Example: Inverter with a Resistive Load Reduction of v O swing due to load resistor PMOS off NMOS off Fig. E4.25
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Common Source Amplifier Preview D D DD DS O R i V v v - = = Large-signal operations Fig. 4.26
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Quiescent Operating Point and Small Signal Operations Large signal (as a function of time) Small signal (as a function of time) Operating point (DC) Fig. 4.28
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Common Emitter Amplifiers in Large and Small Signal Operations Large signal: can use a decoupling capacitance or high-pass filter to obtain the small-signal part only Quiescent point Small signal source Fig. 4.34
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VTC and Voltage Amplification Here we use v o as an output signal. Notice the
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